From 580c5eba79ac28325beaa0df67a2490eef7f78f3 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tristan.gingold@cern.ch>
Date: Mon, 2 May 2022 15:37:30 +0200
Subject: [PATCH] dram: don't scrub during reset, clear memory
---
hdl/rtl/hydra_core.vhd | 11 ++++++++++-
hdl/rtl/hydra_dram.vhd | 13 +++++++------
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/hdl/rtl/hydra_core.vhd b/hdl/rtl/hydra_core.vhd
index 80e67a6..5064ef8 100644
--- a/hdl/rtl/hydra_core.vhd
+++ b/hdl/rtl/hydra_core.vhd
@@ -172,7 +172,13 @@ begin
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
- null;
+ reg_dm_addr <= x"0004_0000";
+ reg_dm_data_s <= (others => '0');
+ reg_dm_data_select <= (others => '1');
+ elsif cpu_rst_n_i = '0' then
+ if dm_done = '1' then
+ reg_dm_addr <= std_logic_vector(unsigned(reg_dm_addr) + 4);
+ end if;
else
if dm_load = '1' or dm_store = '1' then
reg_dm_addr <= dm_addr;
@@ -243,6 +249,7 @@ begin
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
+ cpu_rst_n_i => cpu_rst_n_i,
addr_i => reg_dm_addr(g_DRAM_LOG_SIZE - 1 downto 2),
en_i => reg_dm_en,
we_i => reg_dm_store,
@@ -279,6 +286,8 @@ begin
sv_wb_out.stb <= '0';
reg_dm_load <= '0';
reg_dm_store <= '0';
+ elsif cpu_rst_n_i = '0' then
+ reg_dm_store <= not reg_dm_addr(g_DRAM_LOG_SIZE);
else
if dm_cycle_in_progress = '0' then
-- Data bus was idle.
diff --git a/hdl/rtl/hydra_dram.vhd b/hdl/rtl/hydra_dram.vhd
index f5c9568..ca2ef60 100644
--- a/hdl/rtl/hydra_dram.vhd
+++ b/hdl/rtl/hydra_dram.vhd
@@ -37,6 +37,7 @@ entity hydra_dram is
-- Note: only writes are allowed during reset.
clk_i : in std_logic;
rst_n_i : in std_logic;
+ cpu_rst_n_i : in std_logic;
-- Read port
-- RDONE_O is a pulse.
@@ -86,17 +87,17 @@ begin
-- The raw ram.
p_ram: process (clk_i)
is
- variable iram : t_ram39_type(0 to RAM_WSIZE - 1);
+ variable ram : t_ram39_type(0 to RAM_WSIZE - 1) := (others => (others => '1'));
variable d : std_logic_vector(38 downto 0);
variable err : std_logic_vector(38 downto 0) := (0 => '1', others => '0');
variable sim_cnt : natural;
begin
if rising_edge(clk_i) then
if wen = '1' then
- iram (to_integer(unsigned(addr))) := wdata_ecc;
+ ram (to_integer(unsigned(addr))) := wdata_ecc;
end if;
if ren = '1' then
- d := iram (to_integer(unsigned(addr)));
+ d := ram (to_integer(unsigned(addr)));
-- Simulate errors.
if g_SIM_SEU_PERIOD /= 0 then
@@ -151,7 +152,7 @@ begin
end process;
p_ctrl: process (state,
- p_done, r_done, scrub_done, rerr,
+ p_done, r_done, scrub_done, rerr,
rerr_one, rdata_ecc, rsyndrome, last_addr, last_we, last_sel, recc,
en_i, addr_i, we_i, data_i, r_done_d,
scrub_rd, scrub_addr, scrub_done_d, rst_n_i)
@@ -186,7 +187,7 @@ begin
else
-- Uncorrectable. Just recompute the ECC to be able to continue.
n_ecc_fatal <= '1';
- wdata_ecc <= rdata_ecc;
+ wdata_ecc <= recc & rdata_ecc(31 downto 0);
end if;
addr <= last_addr;
wen <= '1';
@@ -236,7 +237,7 @@ begin
ren <= '1';
n_r_done <= '1';
end if;
- elsif rst_n_i = '1' then
+ elsif cpu_rst_n_i = '1' then
-- scrub if idle (but not during reset)
addr <= scrub_addr;
ren <= '1';
--
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