diff --git a/hdl/rtl/hydra_core.vhd b/hdl/rtl/hydra_core.vhd
index 86651f8079c2f84faacb5075c829fae2e2c3d182..5a89bd963e553028e9cc86bfdc906fe0dd448ee4 100644
--- a/hdl/rtl/hydra_core.vhd
+++ b/hdl/rtl/hydra_core.vhd
@@ -53,6 +53,9 @@ entity hydra_core is
     iram_data_i : in  std_logic_vector(31 downto 0);
     iram_ecc_i  : in  std_logic_vector(6 downto 0);
 
+    -- Set to clear DRAM while cpu reset.
+    dram_clr_i  : in  std_logic;
+
     cpu_err_o : out std_logic
   );
 end hydra_core;
@@ -311,7 +314,7 @@ begin
         sv_wb_out.stb        <= '0';
         reg_dm_load          <= '0';
         reg_dm_store         <= '0';
-      elsif cpu_rst_n_i = '0' then
+      elsif cpu_rst_n_i = '0' and dram_clr_i = '1' then
         --  Write to dram until the last address.
         reg_dm_store <= not reg_dm_addr(g_DRAM_LOG_SIZE);
       else