diff --git a/hdl/syn/sf2-test/pnr_clocks.sdc b/hdl/syn/sf2-test/pnr_clocks.sdc
index 3a54a596c6c6b635dd84bcac7cee1b3e1e723fe2..318eeef5c805bdc293e803249262b9ffb5fcc37a 100644
--- a/hdl/syn/sf2-test/pnr_clocks.sdc
+++ b/hdl/syn/sf2-test/pnr_clocks.sdc
@@ -1 +1 @@
-create_clock -name clk -period 10 -waveform {0 5 } -add [ get_pins { inst_uart.FCCC_C0_0.FCCC_C0_0.CCC_INST/GL0 } ]
+create_clock -name clk -period 20 -waveform {0 10 } -add [ get_pins { inst_uart.FCCC_C0_0.FCCC_C0_0.CCC_INST/GL0 } ]
diff --git a/hdl/syn/sf2-test/syn_clocks.sdc b/hdl/syn/sf2-test/syn_clocks.sdc
index 0173e666f439dc8757ee440eb35fb0ce40fd3a10..a4e75011235aa86ca445e63030f5fba7b668573e 100644
--- a/hdl/syn/sf2-test/syn_clocks.sdc
+++ b/hdl/syn/sf2-test/syn_clocks.sdc
@@ -3,4 +3,4 @@
# inst_uart.FCCC_C0_0.FCCC_C0_0.GL0_INST
-create_clock -period 10 [ get_pins { inst_uart/FCCC_C0_0/FCCC_C0_0/CCC_INST/GL0 } ]
+create_clock -period 20 [ get_pins { inst_uart/FCCC_C0_0/FCCC_C0_0/CCC_INST/GL0 } ]
diff --git a/hdl/top/sf2-test/FCCC_C0.vhd b/hdl/top/sf2-test/FCCC_C0.vhd
index bfafbc0db884173c83c5516171aec781b2446aa5..ad80f478a0f057b296b0d5abdbc8195cc4e14edd 100644
--- a/hdl/top/sf2-test/FCCC_C0.vhd
+++ b/hdl/top/sf2-test/FCCC_C0.vhd
@@ -1,5 +1,5 @@
----------------------------------------------------------------------
--- Created by SmartDesign Thu Nov 18 13:58:29 2021
+-- Created by SmartDesign Wed May 4 16:45:19 2022
-- Version: v2021.2 2021.2.0.11
----------------------------------------------------------------------
@@ -25,12 +25,12 @@
--"GL0_BP_IN_0_SRC:IO_HARDWIRED_0" \
--"GL0_BP_IN_1_FREQ:100" \
--"GL0_BP_IN_1_SRC:IO_HARDWIRED_0" \
---"GL0_FREQUENCY_LOCKED:false" \
+--"GL0_FREQUENCY_LOCKED:true" \
--"GL0_IN_0_SRC:PLL" \
--"GL0_IN_1_SRC:UNUSED" \
--"GL0_IS_INVERTED:false" \
--"GL0_IS_USED:true" \
---"GL0_OUT_0_FREQ:100" \
+--"GL0_OUT_0_FREQ:50" \
--"GL0_OUT_1_FREQ:50" \
--"GL0_OUT_IS_GATED:false" \
--"GL0_PLL_IN_0_PHASE:0" \
@@ -39,12 +39,12 @@
--"GL1_BP_IN_0_SRC:IO_HARDWIRED_0" \
--"GL1_BP_IN_1_FREQ:100" \
--"GL1_BP_IN_1_SRC:IO_HARDWIRED_0" \
---"GL1_FREQUENCY_LOCKED:false" \
+--"GL1_FREQUENCY_LOCKED:true" \
--"GL1_IN_0_SRC:PLL" \
--"GL1_IN_1_SRC:UNUSED" \
--"GL1_IS_INVERTED:false" \
---"GL1_IS_USED:false" \
---"GL1_OUT_0_FREQ:100" \
+--"GL1_IS_USED:true" \
+--"GL1_OUT_0_FREQ:50" \
--"GL1_OUT_1_FREQ:50" \
--"GL1_OUT_IS_GATED:false" \
--"GL1_PLL_IN_0_PHASE:0" \
@@ -53,12 +53,12 @@
--"GL2_BP_IN_0_SRC:IO_HARDWIRED_0" \
--"GL2_BP_IN_1_FREQ:100" \
--"GL2_BP_IN_1_SRC:IO_HARDWIRED_0" \
---"GL2_FREQUENCY_LOCKED:false" \
+--"GL2_FREQUENCY_LOCKED:true" \
--"GL2_IN_0_SRC:PLL" \
--"GL2_IN_1_SRC:UNUSED" \
--"GL2_IS_INVERTED:false" \
---"GL2_IS_USED:false" \
---"GL2_OUT_0_FREQ:100" \
+--"GL2_IS_USED:true" \
+--"GL2_OUT_0_FREQ:50" \
--"GL2_OUT_1_FREQ:50" \
--"GL2_OUT_IS_GATED:false" \
--"GL2_PLL_IN_0_PHASE:0" \
@@ -67,12 +67,12 @@
--"GL3_BP_IN_0_SRC:IO_HARDWIRED_0" \
--"GL3_BP_IN_1_FREQ:100" \
--"GL3_BP_IN_1_SRC:IO_HARDWIRED_0" \
---"GL3_FREQUENCY_LOCKED:false" \
+--"GL3_FREQUENCY_LOCKED:true" \
--"GL3_IN_0_SRC:PLL" \
--"GL3_IN_1_SRC:UNUSED" \
--"GL3_IS_INVERTED:false" \
---"GL3_IS_USED:false" \
---"GL3_OUT_0_FREQ:100" \
+--"GL3_IS_USED:true" \
+--"GL3_OUT_0_FREQ:50" \
--"GL3_OUT_1_FREQ:50" \
--"GL3_OUT_IS_GATED:false" \
--"GL3_PLL_IN_0_PHASE:0" \
@@ -91,7 +91,7 @@
--"GPD3_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
--"GPD_EXPOSE_RESETS:false" \
--"GPD_SYNC_STYLE:G3STYLE_AND_LOCK_RSTSYNC" \
---"INIT:0000007F98000044D74000318C6318C1F18C61E40404040401802" \
+--"INIT:0000007F90000045174000307C1F07C1F18C61E40404040401805" \
--"IO_HARDWIRED_0_IS_DIFF:false" \
--"IO_HARDWIRED_1_IS_DIFF:false" \
--"IO_HARDWIRED_2_IS_DIFF:false" \
@@ -149,6 +149,9 @@ entity FCCC_C0 is
XTLOSC : in std_logic;
-- Outputs
GL0 : out std_logic;
+ GL1 : out std_logic;
+ GL2 : out std_logic;
+ GL3 : out std_logic;
LOCK : out std_logic
);
end FCCC_C0;
@@ -167,6 +170,9 @@ component FCCC_C0_FCCC_C0_0_FCCC
XTLOSC : in std_logic;
-- Outputs
GL0 : out std_logic;
+ GL1 : out std_logic;
+ GL2 : out std_logic;
+ GL3 : out std_logic;
LOCK : out std_logic
);
end component;
@@ -174,8 +180,14 @@ end component;
-- Signal declarations
----------------------------------------------------------------------
signal GL0_net_0 : std_logic;
+signal GL1_net_0 : std_logic;
+signal GL2_net_0 : std_logic;
+signal GL3_net_0 : std_logic;
signal LOCK_net_0 : std_logic;
signal GL0_net_1 : std_logic;
+signal GL1_net_1 : std_logic;
+signal GL2_net_1 : std_logic;
+signal GL3_net_1 : std_logic;
signal LOCK_net_1 : std_logic;
----------------------------------------------------------------------
-- TiedOff Signals
@@ -196,6 +208,12 @@ begin
----------------------------------------------------------------------
GL0_net_1 <= GL0_net_0;
GL0 <= GL0_net_1;
+ GL1_net_1 <= GL1_net_0;
+ GL1 <= GL1_net_1;
+ GL2_net_1 <= GL2_net_0;
+ GL2 <= GL2_net_1;
+ GL3_net_1 <= GL3_net_0;
+ GL3 <= GL3_net_1;
LOCK_net_1 <= LOCK_net_0;
LOCK <= LOCK_net_1;
----------------------------------------------------------------------
@@ -208,6 +226,9 @@ FCCC_C0_0 : FCCC_C0_FCCC_C0_0_FCCC
XTLOSC => XTLOSC,
-- Outputs
GL0 => GL0_net_0,
+ GL1 => GL1_net_0,
+ GL2 => GL2_net_0,
+ GL3 => GL3_net_0,
LOCK => LOCK_net_0
);
diff --git a/hdl/top/sf2-test/FCCC_C0_FCCC_C0_0_FCCC.vhd b/hdl/top/sf2-test/FCCC_C0_FCCC_C0_0_FCCC.vhd
index c5cd27e8b70c40df3a8b030b04a064dda96d7365..bbe6270439aa7cb9ab410b2f9f944e3d17e46740 100644
--- a/hdl/top/sf2-test/FCCC_C0_FCCC_C0_0_FCCC.vhd
+++ b/hdl/top/sf2-test/FCCC_C0_FCCC_C0_0_FCCC.vhd
@@ -9,26 +9,29 @@ entity FCCC_C0_FCCC_C0_0_FCCC is
port( XTLOSC : in std_logic;
LOCK : out std_logic;
- GL0 : out std_logic
+ GL0 : out std_logic;
+ GL1 : out std_logic;
+ GL2 : out std_logic;
+ GL3 : out std_logic
);
end FCCC_C0_FCCC_C0_0_FCCC;
architecture DEF_ARCH of FCCC_C0_FCCC_C0_0_FCCC is
- component VCC
- port( Y : out std_logic
+ component CLKINT
+ port( A : in std_logic := 'U';
+ Y : out std_logic
);
end component;
- component GND
+ component VCC
port( Y : out std_logic
);
end component;
- component CLKINT
- port( A : in std_logic := 'U';
- Y : out std_logic
+ component GND
+ port( Y : out std_logic
);
end component;
@@ -88,24 +91,34 @@ architecture DEF_ARCH of FCCC_C0_FCCC_C0_0_FCCC is
);
end component;
- signal gnd_net, vcc_net, GL0_net : std_logic;
+ signal gnd_net, vcc_net, GL0_net, GL1_net, GL2_net, GL3_net
+ : std_logic;
signal nc8, nc7, nc6, nc2, nc5, nc4, nc3, nc1 : std_logic;
begin
+ GL3_INST : CLKINT
+ port map(A => GL3_net, Y => GL3);
+
+ GL1_INST : CLKINT
+ port map(A => GL1_net, Y => GL1);
+
vcc_inst : VCC
port map(Y => vcc_net);
gnd_inst : GND
port map(Y => gnd_net);
+ GL2_INST : CLKINT
+ port map(A => GL2_net, Y => GL2);
+
GL0_INST : CLKINT
port map(A => GL0_net, Y => GL0);
CCC_INST : CCC
- generic map(INIT => "00" & x"000007F98000044D74000318C6318C1F18C61E40404040401802",
+ generic map(INIT => "00" & x"000007F90000045174000307C1F07C1F18C61E40404040401805",
VCOFREQUENCY => 800.000)
port map(Y0 => OPEN, Y1 => OPEN, Y2 => OPEN, Y3 => OPEN,
@@ -131,9 +144,9 @@ begin
vcc_net, PWDATA(3) => vcc_net, PWDATA(2) => vcc_net,
PWDATA(1) => vcc_net, PWDATA(0) => vcc_net, CLK0_PAD =>
gnd_net, CLK1_PAD => gnd_net, CLK2_PAD => gnd_net,
- CLK3_PAD => gnd_net, GL0 => GL0_net, GL1 => OPEN, GL2 =>
- OPEN, GL3 => OPEN, RCOSC_25_50MHZ => gnd_net, RCOSC_1MHZ
- => gnd_net, XTLOSC => XTLOSC);
+ CLK3_PAD => gnd_net, GL0 => GL0_net, GL1 => GL1_net, GL2
+ => GL2_net, GL3 => GL3_net, RCOSC_25_50MHZ => gnd_net,
+ RCOSC_1MHZ => gnd_net, XTLOSC => XTLOSC);
end DEF_ARCH;
diff --git a/hdl/top/sf2-test/uart.vhd b/hdl/top/sf2-test/uart.vhd
index 1f5436fadd1b07a4814182e8d869b95e225fc766..8d4509ea3cc46c9b5b0c48362fc42bbf8cc18b2b 100644
--- a/hdl/top/sf2-test/uart.vhd
+++ b/hdl/top/sf2-test/uart.vhd
@@ -54,6 +54,9 @@ component FCCC_C0
XTLOSC : in std_logic;
-- Outputs
GL0 : out std_logic;
+ GL1 : out std_logic;
+ GL2 : out std_logic;
+ GL3 : out std_logic;
LOCK : out std_logic
);
end component;
diff --git a/hdl/top/sf2-test/uart_MSS.vhd b/hdl/top/sf2-test/uart_MSS.vhd
index 45c688645eb03d731f056bd02f6c20a98dbc5efe..087ff11761429949b4d7f5864db70a3ea95ac362 100644
--- a/hdl/top/sf2-test/uart_MSS.vhd
+++ b/hdl/top/sf2-test/uart_MSS.vhd
@@ -872,8 +872,8 @@ MMUART_0_TXD_PAD : TRIBUFF
MSS_ADLIB_INST : MSS_050
generic map(
ACT_UBITS => ( x"FFFFFFFFFFFFFF" ),
- DDR_CLK_FREQ => ( 100.0 ),
- INIT => ( "0" & x"0000000001B090000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007800000007800000000000000000000000000000003FFFFFFFD800000803C33C000000007092C0104003FFFFE400000000000010000000000E11C000001FE5FC4010842108421000001FE34001FF8000000400000000020091007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" ),
+ DDR_CLK_FREQ => ( 50.0 ),
+ INIT => ( "0" & x"0000000001B090000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007800000007800000000000000000000000000000003FFFFFFFD800000803C33C00000000709300000003FFFFE400000000000010000000000E11C000001FE5FC4010842108421000001FE34001FF8000000400000000020051007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" ),
MEMORYFILE => ( "ENVM_init.mem" ),
RTC_MAIN_XTL_FREQ => ( 0.0 ),
RTC_MAIN_XTL_MODE => ( "" )