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Last edited by Peter Jansweijer Apr 13, 2021
Page history

High Precision Secondary External Clock (HPSEC)

Project description

The aim of this project is to upgrade the performance of White Rabbit devices to a level suitable for the Metrology purposes by interfacing the White Rabbit devices to a high precision, ultra stable 10 MHz Oven Controlled Crystal Oscillator (OCXO). Metrology institutes may use the HPSEC to make remote copies of their atomic timescales, hence one could translate HPSEC into High Precision Second.

Ultra stable Oven Controlled Crystal Oscillators typically reach their stability only after a couple of days. Therefore the oscillator is never switched off and has a very clean 12V power supply. A separate 24V input that can connect to an Uninterruptible Power Supply (UPS) to prevent 12V oscillator power-down during a power outage. A buffered copy of the oscillator 10 MHz sine wave is available on three front panel connectors.

The oscillator can be disciplined via Vtune (0-5V) by a DAC which is controlled via an SPI-bus.

The oscillator 10MHz sine wave is fed to two Phase Locked Loop (PLL) Circuits (see Figure 3):

  • The first circuit is a Phase Locked Oscillator (PLO) that generates a low phase noise 1 GHz. The PLO is composed of a HMC704 PLL and 1 GHz SAW Oscillator. A divide by 8 or 16 creates a 125/62.5 MHz output clock. White Rabbit devices interface to the HPSEC via this 125/62.5 MHz clock output which is disciplined by the 16-bit SPI DAC interface.
  • The second circuit consists of a chain of two Phase Locked Loops that generate 100 MHz (HMC1031) and 1 GHz (HMC835). The HMC835 can be initialized to generate an arbitrary frequency locked to WR.

The SPEC7 is a typical White Rabbit device which can be upgraded with this HPSEC. The main board contains PCIe connector that fits the SPEC7 and powers the SPEC7 via the PCI bus. High speed D Flip Flops re-sample the 10MHz and 1 PPS signals form the White Rabbit device with the low phase noise 1 GHz clock.

A mezzanine card with a Micro Controller Unit (MCU ARM-M4) serves as a house keeping controller. It has an Ethernet and USB interface. Both Phase Lock Loops (HMC704 and HMC835) can be controlled via the MCU and status information can be retrieved.

All digital interfaces are galvanically isolated from the analog domain to avoid injection of digital noise into the oscillator and PLL circuits.

Figure 1 shows a picture of the 19 inch crate that contains the main oscillator board. The project is currently under development so this is a preliminary picture.

MG_3989_Bewerkt Figure 1: HPSEC.

HPSEC_FrontPanel Figure 2: HPSEC Front Pannel.


Main Features

Figure 3 shows a block diagram of the HPSEC.

HPSEC_BlockDiagram_lostPPS
Figure 3: High Precision Secondary External Clock block diagram.

  • Power supply system with a separate input for a 24V Uninterruptible Power Supply (UPS)
  • ultra stable 10MHz Oven Controlled Crystal Oscillator (OCXO)
    • typically used: Morion MV336
  • Three 10 MHz Sine wave output on TNC connector (J20, J21, J22)
  • 100 MHz LVPECL front panel output on 2 SMA connectors (J154/J155)
  • Arbitrary frequency available on N connector (J25)
  • Possibility to feed external 10 MHz sine wave on the rear panel (J23)
  • Possibility to feed external 1 GHz on the rear panel (J24). This enables to a White Rabbit Grand Master to lock on an external time scale.
  • Two differential LVPECL 125/62.5 MHz SMA outputs on the front panel (J16, J17, J90, J91)
  • Two differential LVPECL 1 GHz SMA outputs on the front panel (J19, J18, J88, J87)
  • Two D-FlipFlop re-sample circuits to clean the White Rabbit device differential 10MHz and PPS outputs
    • 10 MHz input (from WR device). Connectors J13, J12, internal on the main board
    • 10 MHz output LVPECL SMA front panel connectors (J8, J9)
    • PPS input (from WR device). Connectors J15, J14, internal on the main board
    • PPS output LVPECL SMA front panel connectors (J10, J11)
  • Differential LVDS SPI interface on rear panel (J143 internally galvanic isolated)
  • Rear panel Ethernet 10/100 Mb interface (J69, RJ45)
  • Front panel mini-USB (J70)
  • Various internal debug and monitor connectors (J1001, J94, J7).
  • Lost PPS generates 1 PPS from 125/62.5 MHz input when HPSEC is used as Grand Master.

Performance

Phasenoise10MHz_WR_WRJL_FREE Figure 4: 10MHz output Phase Noise performance.

10MHzHPSEC_LongRum_WRLJ Figure 5: Allen Deviation.


Project information

  • Official production documentation

    • Schematics (Note: Design created with Mentor Graphics using a Xpedition).
    • Preliminary HPSEC Documentation v1.3
    • Manufacturing files 11300.05.02_HPSEC.zip (Note: PCB Design created with Mentor Graphics using a Xpedition License)
    • LostPPS wiki
    • Manufacturing files 11300.03.0_LOSTPPS.rar (Note: PCB Design created with Mentor Graphics using a Xpedition License)
    • Manufacturing files 11300.06.01_FMC_WRITE_MOD_HPSEC_-_Corrected.rar (Note: PCB Design created with Mentor Graphics using a Xpedition License)
  • This work is partially funded by the EMPIR 17IND14 WRITE project and the project has received funding from the EMPIR programme co-financed by the Participating States and from the European Union’s Horizon 2020 research and innovation programme.

empir write-logo-trans

Contacts

Commercial producers

  • The board will be quite expensive and tailored for extreme precision which is usually beyond the specifications needed by ordinary users. Therefore it is not foreseen that the board will be commercially available.

General questions about project

  • Guido Visser, Peter Jansweijer - Nikhef

Status

Date Event
01-07-2019 Start working on project. Collecting main specifications.
27-09-2019 Schematics ready to be reviewed.
27-09-2019 Layout started (in parallel).
14-11-2019 Schematics reviewed by Peter Jansweijer and Hans Verkooijen (Nikhef).
28-04-2020 Layout complete.
22-07-2020 2 assembled PCB's received.
01-09-2020 Minor issues, hardware tests okay! Oscillator control loop needs optimization => further study.
10-03-2021 add design files, update documentation.
19-03-2021 update documentation v1.2.
13-04-2021 update documentation v1.3 (errata Allen Deviation).

13 April 2021

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