We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 31.25 kHz 18-bits by the Analog Devices AD7982.
| Low cost | Less than 5000 U$D per unit for small volume production |
| High sensitivity and <br>dynamic range | An input referred voltage noise of about 3 uV or less, <br>and 18-bits data acquisition possible |
| Hardware modularity <br>and standardization | Adopted the FMC VITA 57 standard format for <br>a single mezzanine FPGA module. <br>Being a standard FMC-LPC module, it is possible to <br>manage it from any commercial FMC carrier |
| High sampling rate | Maximum of 31.25 kS/sec on all 128 channels, <br>and up to 1 MS/sec on any four channels of <br>distinct 32-channels banks |
| Facility for high <br>throughput and low <br>latency data processing | Adopted the FMC module standard format to <br>allow real time data acquisition and processing of <br>the input data stream by mean of a medium/high <br>performance FPGA resident in an FMC carrier |
We have developed two versions of HiCCE-128-FMC boards and preliminary results showed promising performance.
#### Publications
some of related publications are listed here.
[1] A. Cicuttin, M. L. Crespo, K. S. Mannatunga, J. G. Samarawickrama,
K. M. Khare, S. Abeytunge, M. B. I. Reaz, and M. O. Magnasco, “HiCCE- 128: An open hardware FMC module for High-Channel Count Electrophysiology,” in 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES). IEEE, 2016, pp. 11–16.
[2] K. S. Mannatunga, L. G. Ordóñez, M. B. Amador, M. L. Crespo, A. Cicuttin, S. Levorato, R. Melo, and B. Valinoti, “Design for Portability of Reconfigurable Virtual Instrumentation,” in 2019 X Southern Conference on Programmable Logic (SPL). IEEE, 2019, pp. 45–52.
[3] A. Cicuttin, M. L. Crespo, K. S. Mannatunga, J. G. Samarawickrama, N. Abdallah, and P. B. Sabet, “HyperFPGA: A possible general purpose reconfigurable hardware for custom supercomputing,” in 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), 2016, pp. 21–26.
[4] O. Adeluyi, M. L. Crespo, A. Cicuttin, and M. Risco-Castillo, “Reconfigurable standard and Ad-hoc instrumentation using an FPGA platform,” FPGAWorld 2010, 2010.
[5] A. Cicuttin, M. L. Crespo, A. Shapiro, and N. Abdallah, “Building an
evolvable low-cost hw/sw educational platform–application to virtual instrumentation,” in 2007 IEEE International Conference on Microelectronic
Systems Education (MSE’07), June 2007, pp. 77–78.
[6] A. Cicuttin, M. L. Crespo, A. Shapiro, and N. Abdallah, “A blockbased open source approach for a reconfigurable virtual instrumentation
platform using fpga technology,” in 2006 IEEE International Conference on Reconfigurable Computing and FPGA’s (ReConFig 2006). IEEE,
