SoC design files added

37da68b8 · Kasun Sameera Mannatunga · 24f8a60f · 37da68b8 · 37da68b8 · 37da68b8
Commit 37da68b8 authored May 24, 2020 by Kasun Sameera Mannatunga
28 changed files
--- a/SoC firmware/Bitstreams/HiCCEv2_pre_built_zedboard.bit
+++ b/SoC firmware/Bitstreams/HiCCEv2_pre_built_zedboard.bit
--- a/SoC firmware/Bitstreams/HiCCEv2_pre_built_zedboard.elf
+++ b/SoC firmware/Bitstreams/HiCCEv2_pre_built_zedboard.elf
--- a/SoC firmware/Bitstreams/fsbl.elf
+++ b/SoC firmware/Bitstreams/fsbl.elf
--- a/SoC firmware/Constraints/HiCCEv2_const.xdc
+++ b/SoC firmware/Constraints/HiCCEv2_const.xdc
--- a/SoC firmware/README.md
+++ b/SoC firmware/README.md
+# SoC firmware for HiCCE
+
+__Folder structure__
+
+* Bitstreams    - Pre built bitstream, ARM processor executables, etc.  
+* Constraints   - Constraints file for HiCCE used in Xilinx's Vivado (XDC file - Xilinx Design Constraints file)
+* ip_repo       - Custom Vivado IP repository
+* SoChw         - Tcl files to recreate Vivado project
+* SoCsdk        - C files to use with the Vivado SDK project
+
+
+__Requirements:__
+* Vivado 2019.1
+
+
+__Instructions:__
+1. You can use pre-built files to create a boot image and execute in the SD card. These files were generated for Avnet ZedBoard.
+
+2. You can create a fresh project using other files provided with this repo.
+  * Create a project with the desired board (eg. ZedBoard)
+  * Add ip_repo path to the project
+  * Add Constraints files to the project
+  * Run in the Tcl console the command source ~filename.tcl
+  * Create a hdl wrapper for the design
+  * Generate the Bitstream for the design
+  * Export Hardware (include the Bitstream)
+  * Launch the SDK
+  * Create a new baremetal/FreeRtos application
+  * Add appropriate files under the SoCsdk folder
+  * Program the FPGA Bitstream, and run the software app(PS)
--- a/SoC firmware/SoChw/HiCCEv2.tcl
+++ b/SoC firmware/SoChw/HiCCEv2.tcl
--- a/SoC firmware/SoCsdk/FreeRTOS/ARM_CommBlock_v1.c
+++ b/SoC firmware/SoCsdk/FreeRTOS/ARM_CommBlock_v1.c
+/*
+ * ARM_CommBlock_v1.c
+ *
+ *  Created on: Aug 26, 2018
+ *      Author: Kasun
+ */
+#include <string.h>
+#include <stdlib.h>
+#include "xil_io.h"
+#include "ARM_CommBlock_v1.h"
+#include "FPGA_CommBlock_v1.h"
+
+char *command;
+char *pch;		// local variable
+int size = 0;
+
+
+/******************************************************************************
+ * Analyze PC request
+ * ****************************************************************************/
+xPacaket Analyze_PC_request(char *eth_rx_payload){
+
+#if ARM_COMMBLOCK_DEBUG == 1
+	xil_printf("recived = %s\r\n", eth_rx_payload);
+#endif
+	pch= strtok(eth_rx_payload,",");
+	char *word_clave= pch;			// first word is a identifier
+#if ARM_COMMBLOCK_DEBUG == 1
+	xil_printf("1st word = %s\r\n", word_clave);
+#endif
+	pch = strtok(NULL, ",");
+	size= atoi(pch);			// second field if the size
+	// read all the things (for example register numbers)
+//	u32 addr[size];
+	for(int i=0; i<size; i++){
+		pch = strtok(NULL, ",");
+		addr[i]=atoi(pch);
+	  }
+
+	// read the values corresponding to the previous field
+	pch = strtok(NULL, ",");
+	command = pch;					// read the command: read_reg, write_reg, etc
+#if ARM_COMMBLOCK_DEBUG == 1
+	xil_printf("command = %s\r\n", command);
+#endif
+	for(int i=0; i<size; i++){
+		pch = strtok(NULL, ",");
+		values[i]=atoi(pch);
+	}
+
+	xPacaket rtnPack;
+	rtnPack.size = size;
+	rtnPack.addr = addr;
+	rtnPack.values = values;
+	rtnPack.cmd = command;
+
+	return rtnPack;
+}
+
+
+/*****************************************************************************
+ * Exacute PC request
+ *****************************************************************************/
+
+txPacket Execute_PC_request(xPacaket *rxpack){
+	txPacket return_pack;
+	static char *command;
+	unsigned int *tmpaddr, *tmpvalues;
+	int tmpsize;
+
+	command = rxpack->cmd;
+	tmpaddr = rxpack->addr;
+	tmpvalues = rxpack->values;
+	tmpsize = rxpack->size;
+
+#if ARM_COMMBLOCK_DEBUG == 1
+	xil_printf("execute cmd = %s\n", command);
+#endif
+
+	if(strncmp(command, "read_reg", 8) == 0){
+
+	}
+	else if(strncmp(command, "write_reg", 9) == 0){
+		Write_registers(tmpaddr, tmpvalues, tmpsize);
+		return_pack.len = 0;
+		return_pack.txaddr = 0;
+	}
+	else if(strncmp(command, "read_mem", 8) == 0){
+
+	}
+	else if(strncmp(command, "write_mem", 9) == 0){
+
+	}
+	else if(strncmp(command, "read_sfifo", 10) == 0){
+
+		unsigned int addrst = Read_FIFO_Stream(tmpaddr, tmpvalues, tmpsize);
+#if ARM_COMMBLOCK_DEBUG == 1
+		xil_printf("return stream fn = 0x%x\n", addrst);
+#endif
+		return_pack.len = *tmpvalues;
+		return_pack.txaddr = addrst;
+	}
+
+
+
+	else if(strncmp(command, "write_sfifo", 11) == 0){
+
+	}
+	else if(strncmp(command, "stop", 4) == 0){
+		xil_printf("receive cmd = stop \n\r");
+		strvar = "stop";
+//		eTxCnt = 0;
+	}
+	else if(strncmp(command, "arm_stop", 8) == 0){
+		xil_printf("receive cmd = arm_stop \n\r");
+//		gloablStr = "arm_stop";
+		strvar = "stop";
+//		eTxCnt = 0;
+	}
+
+	return return_pack;
+}
+
+
--- a/SoC firmware/SoCsdk/FreeRTOS/ARM_CommBlock_v1.h
+++ b/SoC firmware/SoCsdk/FreeRTOS/ARM_CommBlock_v1.h
+/*
+ * ARM_CommBlock_v1.h
+ *
+ *  Created on: Aug 26, 2018
+ *      Author: Kasun
+ */
+
+#ifndef SRC_ARM_COMMBLOCK_V1_H_
+#define SRC_ARM_COMMBLOCK_V1_H_
+
+#define ARM_COMMBLOCK_DEBUG	0
+
+//#include "project_para.h"
+//#include <stdlib.h>
+
+typedef struct xPacaket{
+	unsigned int	size;
+	unsigned int	*addr;
+	unsigned int	*values;
+	char			*cmd;
+} xPacaket;
+
+typedef struct txPacket{
+	int len;
+	unsigned int txaddr;
+} txPacket;
+
+xPacaket Analyze_PC_request(char *eth_rx_payload);
+txPacket Execute_PC_request(xPacaket *rxpack);
+
+
+
+
+//volatile u8* cur_buf;
+char *strvar;
+
+
+
+#define nReg_readOnly	16
+#define nReg_writeOnly	16
+unsigned int addr[nReg_writeOnly];		//global
+unsigned int values[nReg_writeOnly];			// variable that holds the values
+
+
+
+
+#endif /* SRC_ARM_COMMBLOCK_V1_H_ */
--- a/SoC firmware/SoCsdk/FreeRTOS/DMA.c
+++ b/SoC firmware/SoCsdk/FreeRTOS/DMA.c
+/*
+ * DMA.c
+ *
+ *  Created on: Feb 20, 2017
+ *      Author: Kasun
+ */
+#include "DMA.h"
+
+int DMA_init(unsigned int PKT_LEN_WORDS){
+	Xil_Out32(PACKET_LENGTH_BASEADDR, PKT_LEN_WORDS);
+
+	int Status;
+	XAxiDma_Config *CfgPtr;
+
+	u16 DeviceId = DMA_DEV_ID;
+
+	/* Initialize the XAxiDma device.*/
+	CfgPtr = XAxiDma_LookupConfig(DeviceId);
+	if (!CfgPtr) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+	Status = XAxiDma_CfgInitialize(AxiDma, CfgPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+	if(XAxiDma_HasSg(AxiDma)){
+		xil_printf("Device configured as SG mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Disable interrupts, we use polling mode*/
+	XAxiDma_IntrDisable(AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DEVICE_TO_DMA);
+
+
+	/* Test finishes successfully */
+	return XST_SUCCESS;
+}
+
+
+int DMA_Transfer(unsigned int Intan_RX_BUF_BASE, unsigned int PKT_LEN_BYTES){
+	int Status;
+	u8 *RxBufferPtr;
+	//RxBufferPtr = (u32 *)RX_BUFFER_BASE;
+	RxBufferPtr = (u8 *)Intan_RX_BUF_BASE;
+	//xil_printf("RxBufferPtr = 0x%x, %d\r\n", RxBufferPtr, XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA));
+
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache is enabled */
+	Xil_DCacheFlushRange((u32) RxBufferPtr, PKT_LEN_BYTES);
+
+	Status = XAxiDma_SimpleTransfer(AxiDma,(u32) RxBufferPtr, PKT_LEN_BYTES, XAXIDMA_DEVICE_TO_DMA);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	while (XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA)) {
+		/* Wait */
+	}
+//	xil_printf("DMA transfer completed \r\n");
+	return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+#ifdef CHECK_DATA
+static int CheckData(void){
+	u32 *RxPacket;
+	int Index = 0;
+	volatile u32 *Rx_k = *(volatile u32 (*)[MAX_PKT_LEN])(RX_BUFFER_BASE+4*MAX_PKT_LEN*n);
+
+
+	RxPacket = (u32 *) RX_BUFFER_BASE;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+	Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN);
+
+	xil_printf("Data received: ");
+	for(Index = 0; Index < 32; Index++) {
+		xil_printf("0x%X ", (unsigned int)Rx_k[Index]);
+	}
+	xil_printf("\r\n");
+
+	return XST_SUCCESS;
+}
+#endif
+
+/*
+ * following code snippet can be used for mimic the DMA transfer for Ethernet debugging
+ * x is a random variable whose numbers are between 0 to 1000
+ */
+void DMA_Tranfer_sim(unsigned int DMA_addr, int DMA_size){
+	int i;
+	int x = 0;
+	int dsize = DMA_size/4;
+
+	for(i = 0; i < dsize; i++){
+		x = rand()%1000;
+		Xil_Out32(DMA_addr+4*i,i+x);
+	}
+}
--- a/SoC firmware/SoCsdk/FreeRTOS/DMA.h
+++ b/SoC firmware/SoCsdk/FreeRTOS/DMA.h
+/*
+ * DMA.h
+ *
+ *  Created on: Feb 20, 2017
+ *      Author: Kasun
+ */
+
+#ifndef SRC_DMA_H_
+#define SRC_DMA_H_
+
+#include <stdio.h>
+//#include "platform.h"
+#include "xil_printf.h"
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xtime_l.h"
+
+//#define CHECK_DATA
+
+/*
+ * Device hardware build related constants.
+ */
+// *** DMA parameters ****//
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+#define TEST_START_VALUE	0xC
+
+#define NUMBER_OF_TRANSFERS	1
+
+int n;
+
+//**** tlast parameter ****//
+#define PACKET_LENGTH_BASEADDR	XPAR_GPIO_0_BASEADDR
+
+/************************** Function Prototypes ******************************/
+
+int XAxiDma_SimplePollExample(u16 DeviceId);
+#ifdef CHECK_DATA
+static int CheckData(void);
+#endif
+int DMA_init(unsigned int PKT_LEN_WORDS);
+int DMA_Transfer(unsigned int Intan_RX_BUF_BASE, unsigned int PKT_LEN_BYTES);
+void DMA_Tranfer_sim(unsigned int DMA_addr, int DMA_size);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+//static struct XAxiDma *AxiDma;
+XAxiDma *AxiDma;
+
+#endif /* SRC_DMA_H_ */
--- a/SoC firmware/SoCsdk/FreeRTOS/FPGA_CommBlock_v1.c
+++ b/SoC firmware/SoCsdk/FreeRTOS/FPGA_CommBlock_v1.c
+/*
+ * FPGA_CommBlock.c
+ *
+ *  Created on: Sep 8, 2018
+ *      Author: Kasun
+ */
+#include "FPGA_CommBlock_v1.h"
+#include "project_para.h"
+
+void Write_registers(unsigned int* addr, unsigned int* val, unsigned int size){
+//	xil_printf("Write Address %d\n\r", addr[0]);
+//	xil_printf("Write Value %d\n\r", val[0]);
+#if FPGA_COMMBLOCK_DEBUG == 1
+    xil_printf("Number of Addresses %d\n\r",size);
+#endif
+    for(int i=0; i<size; i++){
+
+    	Xil_Out32(reg_block_base_addr + 4*addr[i], val[i]);
+
+    	unsigned int reg_val= Xil_In32(reg_block_base_addr + 4*addr[i]);
+
+#if FPGA_COMMBLOCK_DEBUG == 1
+       xil_printf("Write address %d	 Value written %d\n\r", addr[i], reg_val);
+#endif
+    }
+}
+
+
+unsigned int Read_FIFO_Stream(unsigned int* addr, unsigned int* val, unsigned int size){
+	unsigned int tmpStearmAddr = 0;
+	unsigned int tmpStreamSize = 0;
+#if FPGA_COMMBLOCK_DEBUG == 1
+	xil_printf("Number of Addresses %d\n\r",size);
+#endif
+	for(int i=0; i<size; i++){
+		tmpStearmAddr = fifo_stream_F2A_base_addr+addr[i];
+		tmpStreamSize = val[i];
+#if FPGA_COMMBLOCK_DEBUG == 1
+		xil_printf("FIFO Stream Address 0x%x\n\r", tmpStearmAddr);
+#endif
+//		cur_buf = ( u8* ) FIFO_STREAM_ADDR;
+//		HiCCE_DMA_Tranfer_sim(tmpStearmAddr, tmpStreamSize);
+		HiCCE_DMA_Tranfer(tmpStearmAddr, tmpStreamSize);
+
+	}
+	return tmpStearmAddr;
+}
+
--- a/SoC firmware/SoCsdk/FreeRTOS/FPGA_CommBlock_v1.h
+++ b/SoC firmware/SoCsdk/FreeRTOS/FPGA_CommBlock_v1.h
+/*
+ * FPGA_CommBlock_v1.h
+ *
+ *  Created on: Sep 8, 2018
+ *      Author: Kasun
+ */
+
+#ifndef SRC_FPGA_COMMBLOCK_V1_H_
+#define SRC_FPGA_COMMBLOCK_V1_H_
+
+#define FPGA_COMMBLOCK_DEBUG	0
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+#define MEM_BASE_ADDR					(XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x10000000)
+#define DMA_F2A_BUFFER_BASE				(MEM_BASE_ADDR + 0x00300000)
+#define fifo_stream_F2A_base_addr		(DMA_F2A_BUFFER_BASE)
+
+#define reg_block_base_addr				XPAR_REG_BLOCK_0_S00_AXI_BASEADDR
+
+#define FPGA_FIFO_SIZE_WORDS			1024*32
+#define FPGA_FIFO_SIZE_BYTES			FPGA_FIFO_SIZE_WORDS*4
+
+void Write_registers(unsigned int* addr, unsigned int* val, unsigned int size);
+
+unsigned int Read_FIFO_Stream(unsigned int* addr, unsigned int* val, unsigned int size);
+
+
+#endif /* SRC_FPGA_COMMBLOCK_V1_H_ */
--- a/SoC firmware/SoCsdk/FreeRTOS/echo.c
+++ b/SoC firmware/SoCsdk/FreeRTOS/echo.c
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+
+#include "lwip/sockets.h"
+#include "netif/xadapter.h"
+#include "lwipopts.h"
+#include "xil_printf.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "ARM_CommBlock_v1.h"
+
+#define DEBUG_TASKS	0
+
+
+#define THREAD_STACKSIZE 1024
+static volatile u8* cur_buf = NULL;
+
+static xQueueHandle xQueue = NULL;
+static xQueueHandle xQueueTx = NULL;
+
+u16_t echo_port = 7;
+
+void print_echo_app_header()
+{
+    xil_printf("%20s %6d %s\r\n", "echo server",
+                        echo_port,
+                        "$ telnet <board_ip> 7");
+
+}
+
+/* thread spawned for each connection */
+void Ethernet_Rx_task(void *p)
+{
+	int sd = (int)p;
+	int RECV_BUF_SIZE = 128;
+	char recv_buf[RECV_BUF_SIZE];
+	int n;
+	xPacaket tmpPack;
+
+	xQueue = xQueueCreate(100, sizeof(xPacaket));
+	if(xQueue == NULL){
+		xil_printf("Queue was not created \r\n");
+	}
+
+	while (1) {
+		/* read a max of RECV_BUF_SIZE bytes from socket */
+		if ((n = read(sd, recv_buf, RECV_BUF_SIZE)) < 0) {
+			xil_printf("%s: error reading from socket %d, closing socket\r\n", __FUNCTION__, sd);
+			break;
+		}
+
+		xil_printf("echo recived = %s\r\n", recv_buf);
+
+		if(n > 0){
+			tmpPack = Analyze_PC_request(recv_buf);
+
+#if DEBUG_TASKS == 1
+			xil_printf("xPacket command = %s\n",tmpPack.cmd);
+			xil_printf("xPacket addr = %d\n",*(tmpPack.addr));
+			xil_printf("xPacket values = %d\n",*(tmpPack.values));
+#endif
+
+			if(	xQueueSend(xQueue, ( void * ) &tmpPack, ( TickType_t ) 10) != pdPASS){
+				xil_printf(" Failed to send \r\n");
+			}
+		}
+
+		/* break if client closed connection */
+		if (n <= 0)
+			break;
+
+	}
+
+	/* close connection */
+	close(sd);
+	vTaskDelete(NULL);
+}
+
+
+void Messege_decoding_task(void *p){
+	int sd = (int)p;
+	xPacaket x;
+	txPacket tmptxpack;
+
+
+	xQueueTx = xQueueCreate(100, sizeof(txPacket));
+	if(xQueueTx == NULL){
+		xil_printf("Queue was not created \r\n");
+	}
+
+	while(1){
+		if(uxQueueSpacesAvailable(xQueue) < 100){
+			if(xQueueReceive(xQueue, &x, ( TickType_t ) 10)){
+				tmptxpack = Execute_PC_request(&x);
+
+#if DEBUG_TASKS == 1
+				xil_printf("de-queued x = %s\r\n", x.cmd);
+				xil_printf("return Execute fn(addr) = 0x%x\n", tmptxpack.txaddr);
+				xil_printf("return Execute fn(size) = %d\n", tmptxpack.len);
+#endif
+
+				if(	xQueueSend(xQueueTx, ( void * ) &tmptxpack, ( TickType_t ) 10) != pdPASS){
+					xil_printf(" Failed to send \r\n");
+				}
+
+			}
+			else
+				xil_printf("de-queued failed \r\n");
+		}
+	}
+
+	/* close connection */
+	close(sd);
+	vTaskDelete(NULL);
+}
+
+void Ethernet_Tx_task(void *p){
+	int sd = (int)p;
+	int nwrote;
+	txPacket tmptxpackptr;
+	unsigned int DMA_Buff_addr = 0;
+	int Buff_Size = 0;
+
+	while(1){
+		if(uxQueueSpacesAvailable(xQueueTx) < 100){
+			if(xQueueReceive(xQueueTx, &tmptxpackptr, ( TickType_t ) 10)){
+#if DEBUG_TASKS == 1
+				xil_printf("txPacket in decode (addr) = 0x%x\n", tmptxpackptr.txaddr);
+				xil_printf("txPacket in decode (size) = %d\n", tmptxpackptr.len);
+#endif
+				DMA_Buff_addr = tmptxpackptr.txaddr;
+				Buff_Size = tmptxpackptr.len;
+
+				cur_buf = ( u8* ) DMA_Buff_addr;
+
+#if DEBUG_TASKS == 1
+				xil_printf("cur_buf = 0x%x\n", cur_buf);
+				xil_printf("Buff_Size = %d\n", Buff_Size);
+#endif
+
+				if((Buff_Size >= 0) && (Buff_Size <= 131072)){
+					/* handle request */
+					if ((nwrote = write(sd, (char *) cur_buf, Buff_Size)) < 0) {
+						xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",
+								__FUNCTION__, Buff_Size, nwrote);
+						xil_printf("Closing socket %d\r\n", sd);
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	/* close connection */
+	close(sd);
+	vTaskDelete(NULL);
+}
+
+
+void echo_application_thread()
+{
+	int sock, new_sd;
+	int size;
+#if LWIP_IPV6==0
+	struct sockaddr_in address, remote;
+
+	memset(&address, 0, sizeof(address));
+
+	if ((sock = lwip_socket(AF_INET, SOCK_STREAM, 0)) < 0)
+		return;
+
+	address.sin_family = AF_INET;
+	address.sin_port = htons(echo_port);
+	address.sin_addr.s_addr = INADDR_ANY;
+#else
+	struct sockaddr_in6 address, remote;
+
+	memset(&address, 0, sizeof(address));
+
+	address.sin6_len = sizeof(address);
+	address.sin6_family = AF_INET6;
+	address.sin6_port = htons(echo_port);
+
+	memset(&(address.sin6_addr), 0, sizeof(address.sin6_addr));
+
+	if ((sock = lwip_socket(AF_INET6, SOCK_STREAM, 0)) < 0)
+		return;
+#endif
+
+	if (lwip_bind(sock, (struct sockaddr *)&address, sizeof (address)) < 0)
+		return;
+
+	lwip_listen(sock, 0);
+
+	size = sizeof(remote);
+
+	while (1) {
+		if ((new_sd = lwip_accept(sock, (struct sockaddr *)&remote, (socklen_t *)&size)) > 0) {
+			sys_thread_new("ethe_rxs", Ethernet_Rx_task,
+				(void*)new_sd,
+				THREAD_STACKSIZE,
+				DEFAULT_THREAD_PRIO);
+
+			sys_thread_new("msg_decos", Messege_decoding_task,
+				(void*)new_sd,
+				THREAD_STACKSIZE,
+				DEFAULT_THREAD_PRIO);
+			sys_thread_new("ethe_txs", Ethernet_Tx_task,
+				(void*)new_sd,
+				THREAD_STACKSIZE,
+				DEFAULT_THREAD_PRIO);
+		}
+	}
+}
--- a/SoC firmware/SoCsdk/FreeRTOS/func_gen.c
+++ b/SoC firmware/SoCsdk/FreeRTOS/func_gen.c
+//#include "func_gen.h"
+//#include "project_para.h"
+#include "ARM_CommBlock_v1.h"
+#include "xil_types.h"
+#include "xil_io.h"
+
+u32 reg_value;
+u32 reg_val;
+__uint8_t reg1, reg2,reg3,reg4;
+//u32 Read_registers(u32* addr, u32 size)
+//{
+//	xil_printf("este es la addr %d\n\r",addr);
+//   for(int i=0; i<size; i++){
+//   reg_value= Xil_In32(reg_block_base_addr+4* addr[i]);
+//	   xil_printf("este es el reg %d\n",reg_value);
+//	   xil_printf("len reg_value= %d\n", sizeof(reg_value));
+//      trans_buf[i]= reg_value;
+//   }
+// return reg_value;
+//
+//
+//}
+		
+		
+//void Write_registers(u32* addr, u32* val, u32 size)
+//{
+////	xil_printf("Write Address %d\n\r", addr[0]);
+////	xil_printf("Write Value %d\n\r", val[0]);
+//    xil_printf("Number of Addresses %d\n\r",size);
+//    for(int i=0; i<size; i++){
+//
+////    	Xil_Out32(reg_block_base_addr + 4*addr[i], val[i]);
+//
+//    	reg_val= Xil_In32(reg_block_base_addr + 4*addr[i]);
+//
+//       xil_printf("Write address %d	 Value written %d\n\r", addr[i], reg_val);
+//    }
+//
+//}
+//
+//void Read_FIFO_Stream(u32* addr, u32* val, u32 size){
+//	xil_printf("Number of Addresses %d\n\r",size);
+//	for(int i=0; i<size; i++){
+////		FIFO_STREAM_ADDR = INTAN_A_RX_BUF_BASE+addr[i];
+////		cur_buf = ( u8* ) FIFO_STREAM_ADDR;
+////		xil_printf("FIFO Stream Address 0x%x\n\r", FIFO_STREAM_ADDR);
+//	}
+//	if(FIFO_STREAM_ADDR !=0){
+//		xil_printf("Set the variables \n\r");
+//		strvar = "read_sfifo";
+////		eTxCnt = 0;
+//	}
+//
+//}
+
+//
+//void Read_FIFO(u32* addr, u32 size)
+//{  addr= comblock_FIFO_RD;
+//	fifo_status=Xil_In32(comblock_FIFO_STATUS);
+//	xil_printf("fifo_status : %d",fifo_status);
+//   if((fifo_status&0x00000001)!=1){ //Si no esta vacia
+//	   xil_printf("fifo_status 1 ");
+//	for (int var = 0; var < size-1; ++var) {
+//		trans_bufifo[var] = Xil_In32(addr);
+//	 }
+//   }
+//  else{
+//	  xil_printf("fifo_status 0 ");
+//	for (int var = 0; var < size-1; ++var) {
+//	trans_bufifo[var] = 0;
+//	}
+//  }
+//}
+//
+//
+//void Write_FIFO(int addr, int val)
+//{    int tipo;
+//     tipo=addr;
+//     addr= comblock_FIFO_RD;  //Buscar la de write
+//	//Tal vez tenga que preguntar constantemente por la bandera de full
+//	 //if((fifo_status&0x00000001)!=1){ //Si no esta llena, ver el numero que me da estatus de full
+//        if (tipo==0){
+//	  for (int dir=0; dir<=1024; dir++){
+//		Xil_Out32(addr,val);
+//	  }
+//	//}
+//    }
+//        else{
+//            Xil_Out32(addr,val);
+//        	int a;
+//        	a= addr;
+//        	reg_val= Xil_In32(a);
+//			xil_printf("este es el add+diram %x \n\r", a);
+//			xil_printf("este es el reg %d con valor %d \n\r",a, reg_val);
+//
+//        }
+//
+//}
+//
+//void Read_TDRAM(u32* addr, u32 size)
+//{  u32 addrbase= comblock_TDPR_addr+addr[0];
+//xil_printf("este es el addbase%x \n\r", addrbase);
+//   for (int dir=0; dir<=size*4; dir+=4){
+//	   xil_printf("entre en el for \n\r");
+//	   int a;
+//	   a= addrbase+dir;
+//	trans_bufram[dir/4]=Xil_In32(addrbase+dir);
+//	xil_printf("este es el add+dir %x \n\r", a);
+//	xil_printf("este es el reg %d con valor %d \n\r",dir, trans_bufram[dir/4]);
+//    }
+//}
+//
+//void Write_TDRAM(u32 * addr, u32 * val, u32 size)
+//{
+//	u32 addrbase;
+//	addrbase= comblock_TDPR_addr;
+//	if (size == 1){
+//xil_printf("este es el add %x \n\r", addrbase);
+//	 for(int dir=0; dir<=2048*4; dir+=4){
+//		xil_printf("entre en el for\n\r");//ver aqui si lo dejo como size o si multiplico por 4
+//		xil_printf("este es el val \n\r",val[0]);
+//		Xil_Out32(addrbase+dir,val[0]);
+//		xil_printf("ya escribi\n\r");
+//		int a;
+//		a= addrbase+dir;
+//		xil_printf("este es el add+dir %x \n\r", a);
+//		reg_val= Xil_In32(addrbase+ dir);
+//		xil_printf("este es el reg %d con valor %d \n\r",dir, reg_val);
+//	}
+//	}
+//	else{
+//		for (int i=0; i<size*4; i+=4){
+//		Xil_Out32(addrbase+i,val[i/4]);
+//		int a;
+//	    a= addrbase+i;
+//		reg_val= Xil_In32(a);
+//		xil_printf("este es el add+diram %x \n\r", a);
+//		xil_printf("este es el reg %d con valor %d \n\r",i, reg_val);
+//		}
+//	}
+//}
+//
--- a/SoC firmware/SoCsdk/FreeRTOS/func_gen.h
+++ b/SoC firmware/SoCsdk/FreeRTOS/func_gen.h
+
+#include "xil_io.h"
+#include "xparameters.h"
+//#include "comblock_parameters.h"
+
+ //XGpio l_s;
+u32 trans_buf[2048];
+u32 trans_bufram[2048];
+u32 trans_bufifo[2048];
+char prueba;
+int diram;
+u32 fifo_status;
+
+u32 Read_registers(u32* addr, u32 size);
+
+void Write_registers(u32* addr, u32* val, u32 size);
+//void Write_registers(int addr, int val);
+
+void Read_FIFO_Stream(u32* addr, u32* val, u32 size);
+
+void Read_FIFO(u32*addr, u32 size);
+				
+void Write_FIFO(int addr, int val);
+ 		
+void Read_TDRAM(u32* addr, u32 size);
+	
+void Write_TDRAM(u32* addr, u32* val, u32 size);
+	
--- a/SoC firmware/SoCsdk/FreeRTOS/main.c
+++ b/SoC firmware/SoCsdk/FreeRTOS/main.c
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <stdio.h>
+#include "xparameters.h"
+#include "netif/xadapter.h"
+#include "platform_config.h"
+#include "xil_printf.h"
+												// new
+#include "project_para.h"
+
+#if LWIP_IPV6==1
+#include "lwip/ip.h"
+#else
+#if LWIP_DHCP==1
+#include "lwip/dhcp.h"
+#endif
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+int IicPhyReset(void);
+#endif
+#endif
+
+int main_thread();
+void print_echo_app_header();
+void echo_application_thread(void *);
+
+void lwip_init();
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+extern volatile int dhcp_timoutcntr;
+err_t dhcp_start(struct netif *netif);
+#endif
+#endif
+
+#define THREAD_STACKSIZE 1024
+
+static struct netif server_netif;
+struct netif *echo_netif;
+
+#if LWIP_IPV6==1
+void print_ip6(char *msg, ip_addr_t *ip)
+{
+	print(msg);
+	xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
+			IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
+			IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
+}
+
+#else
+void
+print_ip(char *msg, ip_addr_t *ip)
+{
+	xil_printf(msg);
+	xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
+			ip4_addr3(ip), ip4_addr4(ip));
+}
+
+void
+print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
+{
+
+	print_ip("Board IP: ", ip);
+	print_ip("Netmask : ", mask);
+	print_ip("Gateway : ", gw);
+}
+
+#endif
+int main()
+{
+
+// new
+	init_HiCCE();
+	HiCCE_DMA_Tranfer_sim(INTAN_A_RX_BUF_BASE, FPGA_FIFO_SIZE_BYTES);
+
+	sys_thread_new("main_thrd", (void(*)(void*))main_thread, 0,
+	                THREAD_STACKSIZE,
+	                DEFAULT_THREAD_PRIO);
+	vTaskStartScheduler();
+	while(1);
+	return 0;
+}
+
+void network_thread(void *p)
+{
+    struct netif *netif;
+    /* the mac address of the board. this should be unique per board */
+    unsigned char mac_ethernet_address[] = { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 };
+#if LWIP_IPV6==0
+    ip_addr_t ipaddr, netmask, gw;
+#if LWIP_DHCP==1
+    int mscnt = 0;
+#endif
+#endif
+
+    netif = &server_netif;
+
+    xil_printf("\r\n\r\n");
+    xil_printf("-----lwIP Socket Mode Echo server Demo Application ------\r\n");
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==0
+    /* initliaze IP addresses to be used */
+    IP4_ADDR(&ipaddr,  192, 168, 1, 10);
+    IP4_ADDR(&netmask, 255, 255, 255,  0);
+    IP4_ADDR(&gw,      192, 168, 1, 1);
+#endif
+
+    /* print out IP settings of the board */
+
+#if LWIP_DHCP==0
+    print_ip_settings(&ipaddr, &netmask, &gw);
+    /* print all application headers */
+#endif
+
+#if LWIP_DHCP==1
+	ipaddr.addr = 0;
+	gw.addr = 0;
+	netmask.addr = 0;
+#endif
+#endif
+
+#if LWIP_IPV6==0
+    /* Add network interface to the netif_list, and set it as default */
+    if (!xemac_add(netif, &ipaddr, &netmask, &gw, mac_ethernet_address, PLATFORM_EMAC_BASEADDR)) {
+	xil_printf("Error adding N/W interface\r\n");
+	return;
+    }
+#else
+    /* Add network interface to the netif_list, and set it as default */
+    if (!xemac_add(netif, NULL, NULL, NULL, mac_ethernet_address, PLATFORM_EMAC_BASEADDR)) {
+	xil_printf("Error adding N/W interface\r\n");
+	return;
+    }
+
+    netif->ip6_autoconfig_enabled = 1;
+
+    netif_create_ip6_linklocal_address(netif, 1);
+    netif_ip6_addr_set_state(netif, 0, IP6_ADDR_VALID);
+
+    print_ip6("\n\rBoard IPv6 address ", &netif->ip6_addr[0].u_addr.ip6);
+#endif
+
+    netif_set_default(netif);
+
+    /* specify that the network if is up */
+    netif_set_up(netif);
+
+    /* start packet receive thread - required for lwIP operation */
+    sys_thread_new("xemacif_input_thread", (void(*)(void*))xemacif_input_thread, netif,
+            THREAD_STACKSIZE,
+            DEFAULT_THREAD_PRIO);
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+    dhcp_start(netif);
+    while (1) {
+		vTaskDelay(DHCP_FINE_TIMER_MSECS / portTICK_RATE_MS);
+		dhcp_fine_tmr();
+		mscnt += DHCP_FINE_TIMER_MSECS;
+		if (mscnt >= DHCP_COARSE_TIMER_SECS*1000) {
+			dhcp_coarse_tmr();
+			mscnt = 0;
+		}
+	}
+#else
+    xil_printf("\r\n");
+    xil_printf("%20s %6s %s\r\n", "Server", "Port", "Connect With..");
+    xil_printf("%20s %6s %s\r\n", "--------------------", "------", "--------------------");
+
+    print_echo_app_header();
+    xil_printf("\r\n");
+    sys_thread_new("echod", echo_application_thread, 0,
+		THREAD_STACKSIZE,
+		DEFAULT_THREAD_PRIO);
+    vTaskDelete(NULL);
+#endif
+#else
+    print_echo_app_header();
+    xil_printf("\r\n");
+    sys_thread_new("echod",echo_application_thread, 0,
+		THREAD_STACKSIZE,
+		DEFAULT_THREAD_PRIO);
+    vTaskDelete(NULL);
+#endif
+    return;
+}
+
+int main_thread()
+{
+#if LWIP_DHCP==1
+	int mscnt = 0;
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+	IicPhyReset();
+#endif
+
+	/* initialize lwIP before calling sys_thread_new */
+    lwip_init();
+
+    /* any thread using lwIP should be created using sys_thread_new */
+    sys_thread_new("NW_THRD", network_thread, NULL,
+		THREAD_STACKSIZE,
+            DEFAULT_THREAD_PRIO);
+
+#if LWIP_IPV6==0
+#if LWIP_DHCP==1
+    while (1) {
+	vTaskDelay(DHCP_FINE_TIMER_MSECS / portTICK_RATE_MS);
+		if (server_netif.ip_addr.addr) {
+			xil_printf("DHCP request success\r\n");
+			print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw));
+			print_echo_app_header();
+			xil_printf("\r\n");
+			sys_thread_new("echod", echo_application_thread, 0,
+					THREAD_STACKSIZE,
+					DEFAULT_THREAD_PRIO);
+			break;
+		}
+		mscnt += DHCP_FINE_TIMER_MSECS;
+		if (mscnt >= 10000) {
+			xil_printf("ERROR: DHCP request timed out\r\n");
+			xil_printf("Configuring default IP of 192.168.1.10\r\n");
+			IP4_ADDR(&(server_netif.ip_addr),  192, 168, 1, 10);
+			IP4_ADDR(&(server_netif.netmask), 255, 255, 255,  0);
+			IP4_ADDR(&(server_netif.gw),  192, 168, 1, 1);
+			print_ip_settings(&(server_netif.ip_addr), &(server_netif.netmask), &(server_netif.gw));
+			/* print all application headers */
+			xil_printf("\r\n");
+			xil_printf("%20s %6s %s\r\n", "Server", "Port", "Connect With..");
+			xil_printf("%20s %6s %s\r\n", "--------------------", "------", "--------------------");
+
+			print_echo_app_header();
+			xil_printf("\r\n");
+			sys_thread_new("echod", echo_application_thread, 0,
+					THREAD_STACKSIZE,
+					DEFAULT_THREAD_PRIO);
+			break;
+		}
+	}
+#endif
+#endif
+    vTaskDelete(NULL);
+    return 0;
+}
--- a/SoC firmware/SoCsdk/FreeRTOS/project_para.c
+++ b/SoC firmware/SoCsdk/FreeRTOS/project_para.c
+/*
+ * project_para.c
+ *Bit defitiona of the Config registers
+ *|-------------------------------------------------------------------------------------------------------------|
+ *|Bit 12-11 | Bit 10 | Bit 9 |Bit 8 |Bit 7    |Bit 6 	 |Bit 5 	 |Bit 4  |Bit 3   |Bit 2     |Bit 1 |Bit 0  |
+ *|-------------------------------------------------------------------------------------------------------------|
+ *|Band width|settle  |sel4	  |sel3  |sel2/sync|sel1/step|sel0/resetn|test_en|conn_all|Start/Stop|mode	|Virtual|
+ *|-------------------------------------------------------------------------------------------------------------|
+ *bit 12-11 : Band width selection bits
+ *bit 10	: settle
+ *bit 9-5	: sel0_reset, sel1_step, sel2_sync, sel3, sel4
+ *bit 4		: test_en
+ *bit 3		: conn_all
+ *bit 2		: DAQ_Start
+ *bit 1		: mode - (1-Sequential, 0- manual)
+ *bit 0 	: Virtual mode
+ *
+ *
+ *  Created on: Jul 15, 2018
+ *      Author: Kasun
+ */
+#include "project_para.h"
+#include "DMA.h"
+#include "xil_io.h"
+#include "sleep.h"
+//#include "FreeRTOS.h"
+//#include "task.h" // for vTaskDelay
+
+
+void init_HiCCE(void){
+	/* intialize the DMA system*/
+	DMA_init(FPGA_FIFO_SIZE_WORDS);
+
+	/* Following 8 lines written for Auto sequential mode
+		 * if you need manual mode comment these lines
+		*/
+
+	Xil_Out32(Resetn_Soft_reg_addr, 0);	// active low soft reset
+//	vTaskDelay(10);
+	usleep(100);
+
+	Xil_Out32(Resetn_Soft_reg_addr, 1);	// active low soft reset
+//	vTaskDelay(10);
+	usleep(100);
+
+		// reset the counters in intan chips
+		Xil_Out32(config_intan_A_reg_addr, 6150);	// configure intan A
+		Xil_Out32(config_intan_B_reg_addr, 6150);	// configure intan b
+		Xil_Out32(config_intan_C_reg_addr, 6150);	// configure intan c
+		Xil_Out32(config_intan_D_reg_addr, 6150);	// configure intan d
+
+		// remove the reset
+		Xil_Out32(config_intan_A_reg_addr, 6182);	// configure intan A 6246
+		Xil_Out32(config_intan_B_reg_addr, 6182);	// configure intan b
+		Xil_Out32(config_intan_C_reg_addr, 6182);	// configure intan c	6148
+		Xil_Out32(config_intan_D_reg_addr, 6182);	// configure intan d
+
+
+//		/* Following 8 lines written for manual mode
+//		 * if you need Auto sequential mode uncomment these lines and comment above lines
+//		*/
+////		/*
+//		Xil_Out32(config_intan_A_reg_addr, 7172);	// fast settel for trancients
+//		Xil_Out32(config_intan_B_reg_addr, 7172);	// fast settel for trancients
+//		Xil_Out32(config_intan_C_reg_addr, 7172);	// fast settel for trancients
+//		Xil_Out32(config_intan_D_reg_addr, 7172);	// fast settel for trancients
+//
+////		vTaskDelay(10);
+//		usleep(100);
+//
+//		Xil_Out32(config_intan_A_reg_addr, 6148);	// Normal oparation ch 0 - 6276
+//		Xil_Out32(config_intan_B_reg_addr, 6180);	// Normal oparation ch 0
+//		Xil_Out32(config_intan_C_reg_addr, 6148);	// Normal oparation ch 0
+//		Xil_Out32(config_intan_D_reg_addr, 6148);	// Normal oparation ch 0
+////		*/
+
+		Xil_Out32(read_intan_reg_addr, 15);	// select the fifo
+}
+
+void HiCCE_DMA_Tranfer(unsigned int DMA_tmp_addr, unsigned int DMA_trans_size){
+	int INTAN_ACK, SEL_INTAN, n = 0;
+	unsigned int DMA_base = 0;
+
+	do{
+		INTAN_ACK = Xil_In32(Ack_intan_reg_addr);
+#if DEBUG_HICCE == 1
+		xil_printf("INTAN_ACK %d\r\n", INTAN_ACK);
+#endif
+		if(DMA_tmp_addr == INTAN_A_RX_BUF_BASE){
+			n = 3;										// # bits for masking
+			SEL_INTAN = 8;								// set mutiplex to INTAN A
+			DMA_base = INTAN_A_RX_BUF_BASE;
+
+		}else if(DMA_tmp_addr == INTAN_B_RX_BUF_BASE){
+			n = 2;										// # bits for masking
+			SEL_INTAN = 4;								// set mutiplex to INTAN B
+			DMA_base = INTAN_B_RX_BUF_BASE;
+
+		}else if(DMA_tmp_addr == INTAN_C_RX_BUF_BASE){
+			n = 1;										// # bits for masking
+			SEL_INTAN = 2;								// set mutiplex to INTAN D
+			DMA_base = INTAN_C_RX_BUF_BASE;
+
+
+		}else if(DMA_tmp_addr == INTAN_D_RX_BUF_BASE){
+			n = 0;										// # bits for masking
+			SEL_INTAN = 1;								// set mutiplex to INTAN D
+			DMA_base = INTAN_D_RX_BUF_BASE;
+
+
+		}else{
+			n = 3;										// # bits for masking
+			SEL_INTAN = 8;								// set mutiplex to INTAN A
+			DMA_base = INTAN_A_RX_BUF_BASE;
+
+		}
+		INTAN_ACK = (INTAN_ACK>>n) & 1;				// masked the intan A
+
+#if DEBUG_HICCE == 1
+		xil_printf("INTAN_ACK shifted %d\r\n", INTAN_ACK);
+#endif
+
+	}while(INTAN_ACK != 1);
+
+	Xil_Out32(read_intan_reg_addr, SEL_INTAN);
+	usleep(100);
+//	vTaskDelay(10);
+
+#if DEBUG_HICCE == 1
+	xil_printf("DMA_base = 0x%x\r\n", DMA_base);
+	xil_printf("DMA_trans_size = %d\r\n", DMA_trans_size);
+#endif
+
+	// start dma transfer
+	DMA_Transfer(DMA_base, DMA_trans_size);
+
+#if DEBUG_HICCE == 1
+	xil_printf("DMA transfer complete **** \r\n");
+#endif
+
+	// allow to fill again
+	Xil_Out32(read_intan_reg_addr, 15);
+
+}
+
+
+/*
+ * following code snippet can be used for mimic the DMA transfer for Ethernet debugging
+ * x is a random variable whose numbers are between 0 to 1000
+ */
+void HiCCE_DMA_Tranfer_sim(unsigned int DMA_tmp_addr, unsigned int DMA_trans_size){
+	DMA_Tranfer_sim(DMA_tmp_addr, DMA_trans_size);
+}
--- a/SoC firmware/SoCsdk/FreeRTOS/project_para.h
+++ b/SoC firmware/SoCsdk/FreeRTOS/project_para.h
+/*
+ * project_para.h
+ *
+ *  Created on: Jul 15, 2018
+ *      Author: Kasun
+ */
+
+#ifndef SRC_PROJECT_PARA_H_
+#define SRC_PROJECT_PARA_H_
+
+#define HiCCE_DMA_SIMULATION	0
+#define	DEBUG_HICCE				0
+
+#include "xparameters.h"
+#include "FPGA_CommBlock_v1.h"
+#include "sleep.h"
+#include <stdlib.h>
+
+void init_HiCCE(void);
+void HiCCE_DMA_Tranfer(unsigned int DMA_tmp_addr, unsigned int DMA_trans_size);
+void HiCCE_DMA_Tranfer_sim(unsigned int DMA_tmp_addr, unsigned int DMA_trans_size);
+
+#define DMA_RX_BASEADDR			DMA_F2A_BUFFER_BASE
+#define INTAN_A_RX_BUF_BASE		(DMA_RX_BASEADDR)
+#define INTAN_B_RX_BUF_BASE		(DMA_RX_BASEADDR + 0x00020000)
+#define INTAN_C_RX_BUF_BASE		(DMA_RX_BASEADDR + 0x00040000)
+#define INTAN_D_RX_BUF_BASE		(DMA_RX_BASEADDR + 0x00060000)
+
+//********* registers ***********//
+#define reg_block_base_addr				XPAR_REG_BLOCK_0_S00_AXI_BASEADDR
+#define reg_block_WriteOnly_base_addr 	XPAR_REG_BLOCK_0_S00_AXI_BASEADDR
+
+/*
+ * write only registers
+ */
+#define config_intan_A_reg_addr	reg_block_WriteOnly_base_addr+4*0
+#define config_intan_B_reg_addr	reg_block_WriteOnly_base_addr+4*1
+#define config_intan_C_reg_addr reg_block_WriteOnly_base_addr+4*2
+#define config_intan_D_reg_addr reg_block_WriteOnly_base_addr+4*3
+
+#define read_intan_reg_addr		reg_block_WriteOnly_base_addr+4*4
+
+#define Resetn_Soft_reg_addr	reg_block_WriteOnly_base_addr+4*5
+
+/*
+ * Read only registers
+ */
+#define reg_block_ReadOnly_base_addr	XPAR_REG_BLOCK_0_S00_AXI_BASEADDR+4*14
+
+#define Ack_intan_reg_addr				reg_block_ReadOnly_base_addr+4*0		// input for uP
+#define intan_A_DATA_reg_addr			reg_block_ReadOnly_base_addr+4*1		// input for uP
+#define intan_B_DATA_reg_addr			reg_block_ReadOnly_base_addr+4*2		// input for uP
+#define intan_C_DATA_reg_addr			reg_block_ReadOnly_base_addr+4*3		// input for uP
+#define intan_D_DATA_reg_addr			reg_block_ReadOnly_base_addr+4*4		// input for uP
+//#define Digital_Pot_ACK_reg_addr		reg_block_ReadOnly_base_addr+4*6		// input for uP
+//#define FIFO_empty_reg_addr				reg_block_ReadOnly_base_addr+4*7		// input for uP
+
+//*********** register values ************//
+
+
+#endif /* SRC_PROJECT_PARA_H_ */
--- a/SoC firmware/SoCsdk/baremetal/DMA.c
+++ b/SoC firmware/SoCsdk/baremetal/DMA.c
+/*
+ * DMA.c
+ *
+ *  Created on: Feb 20, 2017
+ *      Author: Kasun
+ */
+#include "DMA.h"
+
+int DMA_init(void){
+	Xil_Out32(PACKET_LENGTH_BASEADDR, MAX_PKT_LEN_WORDS);
+
+	int Status;
+	XAxiDma_Config *CfgPtr;
+
+	u16 DeviceId = DMA_DEV_ID;
+
+	/* Initialize the XAxiDma device.*/
+	CfgPtr = XAxiDma_LookupConfig(DeviceId);
+	if (!CfgPtr) {
+		xil_printf("No config found for %d\r\n", DeviceId);
+		return XST_FAILURE;
+	}
+	Status = XAxiDma_CfgInitialize(AxiDma, CfgPtr);
+	if (Status != XST_SUCCESS) {
+		xil_printf("Initialization failed %d\r\n", Status);
+		return XST_FAILURE;
+	}
+	if(XAxiDma_HasSg(AxiDma)){
+		xil_printf("Device configured as SG mode \r\n");
+		return XST_FAILURE;
+	}
+
+	/* Disable interrupts, we use polling mode*/
+	XAxiDma_IntrDisable(AxiDma, XAXIDMA_IRQ_ALL_MASK,
+						XAXIDMA_DEVICE_TO_DMA);
+
+
+	/* Test finishes successfully */
+	return XST_SUCCESS;
+}
+
+
+int DMA_Transfer(u32 Intan_RX_BUF_BASE){
+	int Status;
+	u8 *RxBufferPtr;
+	//RxBufferPtr = (u32 *)RX_BUFFER_BASE;
+	RxBufferPtr = (u8 *)Intan_RX_BUF_BASE;
+	//xil_printf("RxBufferPtr = 0x%x, %d\r\n", RxBufferPtr, XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA));
+
+
+	/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache is enabled */
+	Xil_DCacheFlushRange((UINTPTR) RxBufferPtr, MAX_PKT_LEN);
+
+	Status = XAxiDma_SimpleTransfer(AxiDma,(UINTPTR) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	while (XAxiDma_Busy(AxiDma,XAXIDMA_DEVICE_TO_DMA)) {
+		/* Wait */
+	}
+//	xil_printf("DMA transfer completed \r\n");
+	return XST_SUCCESS;
+}
+
+
+/******************************************************************************/
+
+static int CheckData(void){
+	u32 *RxPacket;
+	int Index = 0;
+	volatile u32 *Rx_k = *(volatile u32 (*)[MAX_PKT_LEN])(RX_BUFFER_BASE+4*MAX_PKT_LEN*n);
+
+
+	RxPacket = (u32 *) RX_BUFFER_BASE;
+
+	/* Invalidate the DestBuffer before receiving the data, in case the
+	 * Data Cache is enabled
+	 */
+	Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN);
+
+	xil_printf("Data received: ");
+	for(Index = 0; Index < 32; Index++) {
+		xil_printf("0x%X ", (unsigned int)Rx_k[Index]);
+	}
+	xil_printf("\r\n");
+
+	return XST_SUCCESS;
+}
+
+
+
--- a/SoC firmware/SoCsdk/baremetal/DMA.h
+++ b/SoC firmware/SoCsdk/baremetal/DMA.h
+/*
+ * DMA.h
+ *
+ *  Created on: Feb 20, 2017
+ *      Author: Kasun
+ */
+
+#ifndef SRC_DMA_H_
+#define SRC_DMA_H_
+
+#include <stdio.h>
+#include "platform.h"
+#include "xil_printf.h"
+#include "xaxidma.h"
+#include "xparameters.h"
+#include "xtime_l.h"
+
+/*
+ * Device hardware build related constants.
+ */
+// *** DMA parameters ****//
+#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
+
+////#define MEM_BASE_ADDR		(XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x1000000)
+#define MEM_BASE_ADDR		(XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x10000000)
+//
+//#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00100000)
+#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00300000)
+
+////#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x004FFFFF)
+
+
+#define MAX_PKT_LEN_WORDS	1024*16					// 1020*2 //1024*32
+#define MAX_PKT_LEN			MAX_PKT_LEN_WORDS*4			// actual mem locations each 8 bit
+
+#define TEST_START_VALUE	0xC
+
+#define NUMBER_OF_TRANSFERS	1
+
+int n;
+
+//**** tlast parameter ****//
+#define PACKET_LENGTH_BASEADDR	XPAR_GPIO_0_BASEADDR
+
+/************************** Function Prototypes ******************************/
+
+int XAxiDma_SimplePollExample(u16 DeviceId);
+static int CheckData(void);
+int DMA_init(void);
+int DMA_Transfer(u32 Intan_RX_BUF_BASE);
+
+/************************** Variable Definitions *****************************/
+/*
+ * Device instance definitions
+ */
+static struct XAxiDma *AxiDma;
+//XAxiDma AxiDma;
+XTime tStart, tEnd;
+
+#endif /* SRC_DMA_H_ */
--- a/SoC firmware/SoCsdk/baremetal/echo.c
+++ b/SoC firmware/SoCsdk/baremetal/echo.c
--- a/SoC firmware/SoCsdk/baremetal/main.c
+++ b/SoC firmware/SoCsdk/baremetal/main.c
+/******************************************************************************
+*HiCCE v2
+* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <stdio.h>
+
+#include "xparameters.h"
+#include "project_para.h"
+
+#include "netif/xadapter.h"
+
+#include "platform.h"
+#include "platform_config.h"
+#if defined (__arm__) || defined(__aarch64__)
+#include "xil_printf.h"
+#endif
+
+#include "lwip/tcp.h"
+#include "xil_cache.h"
+
+#if LWIP_DHCP==1
+#include "lwip/dhcp.h"
+#endif
+
+/* defined by each RAW mode application */
+void print_app_header();
+int start_application();
+int transfer_data();
+void tcp_fasttmr(void);
+void tcp_slowtmr(void);
+
+/* missing declaration in lwIP */
+void lwip_init();
+
+#if LWIP_DHCP==1
+extern volatile int dhcp_timoutcntr;
+err_t dhcp_start(struct netif *netif);
+#endif
+
+extern volatile int TcpFastTmrFlag;
+extern volatile int TcpSlowTmrFlag;
+static struct netif server_netif;
+struct netif *echo_netif;
+
+void
+print_ip(char *msg, struct ip_addr *ip) 
+{
+	print(msg);
+	xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip), 
+			ip4_addr3(ip), ip4_addr4(ip));
+}
+
+void
+print_ip_settings(struct ip_addr *ip, struct ip_addr *mask, struct ip_addr *gw)
+{
+
+	print_ip("Board IP: ", ip);
+	print_ip("Netmask : ", mask);
+	print_ip("Gateway : ", gw);
+}
+
+#if defined (__arm__) && !defined (ARMR5)
+#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+int ProgramSi5324(void);
+int ProgramSfpPhy(void);
+#endif
+#endif
+
+#ifdef XPS_BOARD_ZCU102
+#ifdef XPAR_XIICPS_0_DEVICE_ID
+int IicPhyReset(void);
+#endif
+#endif
+
+int main()
+{
+	struct ip_addr ipaddr, netmask, gw;
+
+	/* the mac address of the board. this should be unique per board */
+	unsigned char mac_ethernet_address[] =
+	{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 };
+
+	echo_netif = &server_netif;
+#if defined (__arm__) && !defined (ARMR5)
+#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
+	ProgramSi5324();
+	ProgramSfpPhy();
+#endif
+#endif
+
+/* Define this board specific macro in order perform PHY reset on ZCU102 */
+#ifdef XPS_BOARD_ZCU102
+	IicPhyReset();
+#endif
+
+	init_platform();
+
+#if LWIP_DHCP==1
+    ipaddr.addr = 0;
+	gw.addr = 0;
+	netmask.addr = 0;
+#else
+	/* initliaze IP addresses to be used */
+	IP4_ADDR(&ipaddr,  192, 168,   1, 10);
+	IP4_ADDR(&netmask, 255, 255, 255,  0);
+	IP4_ADDR(&gw,      192, 168,   1,  1);
+#endif	
+	print_app_header();
+
+	lwip_init();
+
+  	/* Add network interface to the netif_list, and set it as default */
+	if (!xemac_add(echo_netif, &ipaddr, &netmask,
+						&gw, mac_ethernet_address,
+						PLATFORM_EMAC_BASEADDR)) {
+		xil_printf("Error adding N/W interface\n\r");
+		return -1;
+	}
+	netif_set_default(echo_netif);
+
+	/* now enable interrupts */
+	platform_enable_interrupts();
+
+	/* specify that the network if is up */
+	netif_set_up(echo_netif);
+
+#if (LWIP_DHCP==1)
+	/* Create a new DHCP client for this interface.
+	 * Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
+	 * the predefined regular intervals after starting the client.
+	 */
+	dhcp_start(echo_netif);
+	dhcp_timoutcntr = 24;
+
+	while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
+		xemacif_input(echo_netif);
+
+	if (dhcp_timoutcntr <= 0) {
+		if ((echo_netif->ip_addr.addr) == 0) {
+			xil_printf("DHCP Timeout\r\n");
+			xil_printf("Configuring default IP of 192.168.1.10\r\n");
+			IP4_ADDR(&(echo_netif->ip_addr),  192, 168,   1, 10);
+			IP4_ADDR(&(echo_netif->netmask), 255, 255, 255,  0);
+			IP4_ADDR(&(echo_netif->gw),      192, 168,   1,  1);
+		}
+	}
+
+	ipaddr.addr = echo_netif->ip_addr.addr;
+	gw.addr = echo_netif->gw.addr;
+	netmask.addr = echo_netif->netmask.addr;
+#endif
+
+	print_ip_settings(&ipaddr, &netmask, &gw);
+
+	/* start the application (web server, rxtest, txtest, etc..) */
+	start_application();
+
+	//initialize the HiCCE DAQ
+	    init_HiCCE();
+	    HiCCE_DMA_Tranfer_sim();		// for simulate the DMA
+	  //  HiCCE_DMA_Tranfer();
+	    xil_printf("initial dma transfer is completed\r\n");
+//
+	/* receive and process packets */
+	while (1) {
+		if (TcpFastTmrFlag) {
+			tcp_fasttmr();
+			TcpFastTmrFlag = 0;
+		}
+		if (TcpSlowTmrFlag) {
+			tcp_slowtmr();
+			TcpSlowTmrFlag = 0;
+		}
+		xemacif_input(echo_netif);
+		transfer_data();
+
+		if(strncmp(gloablStr, "arm_stop", 8) == 0){
+			xil_printf("gloablStr = %s\n\r", gloablStr);
+			break;
+		}
+	}
+  
+	xil_printf("Exit .....\n\r");
+	/* never reached */
+	cleanup_platform();
+
+	return 0;
+}
--- a/SoC firmware/SoCsdk/baremetal/project_para.c
+++ b/SoC firmware/SoCsdk/baremetal/project_para.c
+/*
+ * project_para.c
+ *Bit defitiona of the Config registers
+ *bit 12-11 : Band width selection bits
+ *bit 10	: settle
+ *bit 9-5	: sel0_reset, sel1_step, sel2_sync, sel3, sel4
+ *bit 4		: test_en
+ *bit 3		: conn_all
+ *bit 2		: DAQ_Start
+ *bit 1		: mode - (1-Sequential, 0- manual)
+ *bit 0 	: Virtual mode
+ *
+ *
+ *  Created on: Jul 15, 2018
+ *      Author: Kasun
+ */
+#include "project_para.h"
+
+//********* registers ***********//
+#define reg_block_base_addr	XPAR_REG_BLOCK_0_S00_AXI_BASEADDR
+
+#define config_intan_A_reg_addr	reg_block_base_addr+4*0
+#define config_intan_B_reg_addr	reg_block_base_addr+4*1
+#define config_intan_C_reg_addr reg_block_base_addr+4*2
+#define config_intan_D_reg_addr reg_block_base_addr+4*3
+
+#define read_intan_reg_addr		reg_block_base_addr+4*4
+
+#define Resetn_Soft_reg_addr	reg_block_base_addr+4*5
+
+#define Ack_intan_reg_addr		reg_block_base_addr+4*14		// input for uP
+
+//*********** register values ************//
+
+
+void init_HiCCE(void){
+	/* intialize the DMA system*/
+	DMA_init();
+
+	/* Following 8 lines written for Auto sequential mode
+		 * if you need manual mode comment these lines
+		*/
+
+	Xil_Out32(Resetn_Soft_reg_addr, 0);	// active low soft reset
+	usleep(100);
+	Xil_Out32(Resetn_Soft_reg_addr, 1);	// active low soft reset
+	usleep(100);
+
+		// reset the counters in intan chips
+		Xil_Out32(config_intan_A_reg_addr, 6150);	// configure intan A
+		Xil_Out32(config_intan_B_reg_addr, 6150);	// configure intan b
+		Xil_Out32(config_intan_C_reg_addr, 6150);	// configure intan c
+		Xil_Out32(config_intan_D_reg_addr, 6150);	// configure intan d
+
+		// remove the reset
+		Xil_Out32(config_intan_A_reg_addr, 6182);	// configure intan A 6246
+		Xil_Out32(config_intan_B_reg_addr, 6182);	// configure intan b
+		Xil_Out32(config_intan_C_reg_addr, 6182);	// configure intan c	6148
+		Xil_Out32(config_intan_D_reg_addr, 6182);	// configure intan d
+
+
+		/* Following 8 lines written for manual mode
+		 * if you need Auto sequential mode uncomment these lines and comment above lines
+		*/
+//		/*
+//		Xil_Out32(config_intan_A_reg_addr, 7172);	// fast settel for trancients
+//		Xil_Out32(config_intan_B_reg_addr, 7172);	// fast settel for trancients
+//		Xil_Out32(config_intan_C_reg_addr, 7172);	// fast settel for trancients
+//		Xil_Out32(config_intan_D_reg_addr, 7172);	// fast settel for trancients
+//
+//		usleep(100);
+//
+//		Xil_Out32(config_intan_A_reg_addr, 6148);	// Normal oparation ch 0 - 6276
+//		Xil_Out32(config_intan_B_reg_addr, 6180);	// Normal oparation ch 0
+//		Xil_Out32(config_intan_C_reg_addr, 6148);	// Normal oparation ch 0
+//		Xil_Out32(config_intan_D_reg_addr, 6148);	// Normal oparation ch 0
+//		*/
+
+		Xil_Out32(read_intan_reg_addr, 15);	// select the fifo (B - 4 C = 2)
+}
+
+void init_intan(void){
+	if(strncmp(globalstr_intan, "INTAN_A",7)==0){
+		Xil_Out32(read_intan_reg_addr, 8);
+	}
+	if(strncmp(globalstr_intan, "INTAN_B",7)==0){
+		Xil_Out32(read_intan_reg_addr, 4);
+	}
+	if(strncmp(globalstr_intan, "INTAN_C",7)==0){
+		Xil_Out32(read_intan_reg_addr, 2);
+	}
+	if(strncmp(globalstr_intan, "INTAN_D",7)==0){
+		Xil_Out32(read_intan_reg_addr, 1);
+	}
+	if(strncmp(globalstr_intan, "ALL",3)==0){
+		Xil_Out32(read_intan_reg_addr, 15);
+	}
+	else{
+
+	}
+}
+
+void HiCCE_DMA_Tranfer(void){
+
+
+	// start dma transfer
+	if(strncmp(globalstr_intan, "INTAN_A",7)==0){
+		// set mutiple to INTAN A
+		if(((Xil_In32(Ack_intan_reg_addr))>>3) == 1){
+			xil_printf("FIFO states %d \r\n",Xil_In32(Ack_intan_reg_addr)>>3);}
+		DMA_Transfer(INTAN_A_RX_BUF_BASE);
+		globalstr_intan = "INTAN_A";
+		usleep(100);
+	}
+	else if(strncmp(globalstr_intan, "INTAN_B",7)==0){
+		// set mutiple to INTAN B
+		if(((Xil_In32(Ack_intan_reg_addr))>>2) == 1){
+			xil_printf("FIFO states %d \r\n",Xil_In32(Ack_intan_reg_addr)>>2);
+		}
+		// start dma transfer
+		DMA_Transfer(INTAN_B_RX_BUF_BASE);
+		globalstr_intan = "INTAN_B";
+		usleep(100);
+	}
+	else if(strncmp(globalstr_intan, "INTAN_C",7)==0){
+	// set mutiple to INTAN C
+		if(((Xil_In32(Ack_intan_reg_addr))>>1) == 1){
+			xil_printf("FIFO states %d \r\n",Xil_In32(Ack_intan_reg_addr)>>1);
+		}
+		// start dma transfer
+		XTime_GetTime(&tStart);
+		DMA_Transfer(INTAN_C_RX_BUF_BASE);
+		XTime_GetTime(&tEnd);
+		globalstr_intan = "INTAN_C";
+		usleep(100);
+	////
+	}
+	else if(strncmp(globalstr_intan, "INTAN_D",7)==0){
+	// set mutiple to INTAN D
+		if((Xil_In32(Ack_intan_reg_addr)) == 1){
+			xil_printf("FIFO states %d \r\n",Xil_In32(Ack_intan_reg_addr));
+		}
+		// start dma transfer
+		DMA_Transfer(INTAN_D_RX_BUF_BASE);
+		globalstr_intan = "INTAN_D";
+		usleep(100);
+	}
+	else if(strncmp(globalstr_intan, "ALL",3)==0){
+		Xil_Out32(read_intan_reg_addr, 8);
+		if(((Xil_In32(Ack_intan_reg_addr))>>3) == 1);
+		DMA_Transfer(INTAN_A_RX_BUF_BASE);
+		usleep(10);
+
+		Xil_Out32(read_intan_reg_addr, 4);
+		if(((Xil_In32(Ack_intan_reg_addr))>>2) == 1);
+		DMA_Transfer(INTAN_B_RX_BUF_BASE);
+		usleep(10);
+
+		Xil_Out32(read_intan_reg_addr, 2);
+		if(((Xil_In32(Ack_intan_reg_addr))>>1) == 1);
+		DMA_Transfer(INTAN_C_RX_BUF_BASE);
+		usleep(10);
+
+		Xil_Out32(read_intan_reg_addr, 1);
+		if((Xil_In32(Ack_intan_reg_addr)) == 1);
+		DMA_Transfer(INTAN_D_RX_BUF_BASE);
+		usleep(10);
+
+		globalstr_intan= "ALL";
+	}
+
+
+
+
+
+
+//	printf("Output took %llu clock cycles.\n", 2*(tEnd - tStart));
+//	printf("Output took %.2f us.\n", 1.0 * (tEnd - tStart) / (COUNTS_PER_SECOND/1000000));
+}
+
+void data_gen_ramp(int datasize){
+	int i;
+	/* initialize data buffer being sent */
+	for (i = 0; i < datasize; i++)
+		send_buf[i] = (i % 10) + '0';
+}
+
+/*
+ * following code snippet can be used for mimic the DMA transfer for Ethernet debugging
+ * x is a random variable whose numbers are between 0 to 1000
+ */
+void HiCCE_DMA_Tranfer_sim(void){
+	int i;
+	int x = 0;
+	for(i = 0; i < data_size_words; i++){
+		x = rand()%1000;
+		Xil_Out32(DMA_RX_BASEADDR+4*i,i+x);
+	}
+	globalstr_intan = "INTAN_A";
+	eTxCnt = 0;
+//	xil_printf("Dma Transfer complete .. \n\r");
+}
--- a/SoC firmware/SoCsdk/baremetal/project_para.h
+++ b/SoC firmware/SoCsdk/baremetal/project_para.h
+/*
+ * project_para.h
+ *
+ *  Created on: Jul 15, 2018
+ *      Author: Kasun
+ */
+
+#ifndef SRC_PROJECT_PARA_H_
+#define SRC_PROJECT_PARA_H_
+
+#include "xparameters.h"
+#include "DMA.h"
+#include "sleep.h"
+#include <stdlib.h>
+
+void init_HiCCE(void);
+void init_intan(void);
+void HiCCE_DMA_Tranfer(void);
+void data_gen_ramp(int datasize);
+void HiCCE_DMA_Tranfer_sim(void);
+
+#define DMA_RX_BASEADDR		RX_BUFFER_BASE
+#define INTAN_A_RX_BUF_BASE		(DMA_RX_BASEADDR)
+#define INTAN_B_RX_BUF_BASE		(DMA_RX_BASEADDR + 0x00020000)
+#define INTAN_C_RX_BUF_BASE		(DMA_RX_BASEADDR + 0x00040000)
+#define INTAN_D_RX_BUF_BASE		(DMA_RX_BASEADDR + 0x00060000)
+
+
+#define	data_size_words		MAX_PKT_LEN_WORDS
+#define data_size_bytes		data_size_words*4
+
+#define SEND_BUFSIZE (1024)
+static char send_buf[SEND_BUFSIZE];
+int eTxCnt;
+
+char *gloablStr;
+char *globalstr_intan;
+#define No_KB_Segs	 64	// only Intan A
+//#define No_k_Segs	 512	// all Intans
+
+XTime tStart, tEnd;
+
+
+
+#endif /* SRC_PROJECT_PARA_H_ */
--- a/SoC firmware/ip_repo/HiCCE_2018_1.0.rar
+++ b/SoC firmware/ip_repo/HiCCE_2018_1.0.rar
--- a/SoC firmware/ip_repo/comblock.rar
+++ b/SoC firmware/ip_repo/comblock.rar
--- a/SoC firmware/ip_repo/mux16bit4to1_1.0.rar
+++ b/SoC firmware/ip_repo/mux16bit4to1_1.0.rar
--- a/SoC firmware/ip_repo/tlast_gen_1.0.rar
+++ b/SoC firmware/ip_repo/tlast_gen_1.0.rar