# SoC firmware for HiCCE

__Folder structure__

* Bitstreams    - Pre built bitstream, ARM processor executables, etc.  
* Constraints   - Constraints file for HiCCE used in Xilinx's Vivado (XDC file - Xilinx Design Constraints file)
* ip_repo       - Custom Vivado IP repository
* SoChw         - Tcl files to recreate Vivado project
* SoCsdk        - C files to use with the Vivado SDK project


__Requirements:__
* Vivado 2019.1


__Instructions:__
1. You can use pre-built files to create a boot image and execute in the SD card. These files were generated for Avnet ZedBoard.

2. You can create a fresh project using other files provided with this repo.
  * Create a project with the desired board (eg. ZedBoard)
  * Add ip_repo path to the project
  * Add Constraints files to the project
  * Run in the Tcl console the command source ~filename.tcl
  * Create a hdl wrapper for the design
  * Generate the Bitstream for the design
  * Export Hardware (include the Bitstream)
  * Launch the SDK
  * Create a new baremetal/FreeRtos application
  * Add appropriate files under the SoCsdk folder
  * Program the FPGA Bitstream, and run the software app(PS)
