/*
 * FPGA_CommBlock.c
 *
 *  Created on: Sep 8, 2018
 *      Author: Kasun
 */
#include "FPGA_CommBlock_v1.h"
#include "project_para.h"

void Write_registers(unsigned int* addr, unsigned int* val, unsigned int size){
//	xil_printf("Write Address %d\n\r", addr[0]);
//	xil_printf("Write Value %d\n\r", val[0]);
#if FPGA_COMMBLOCK_DEBUG == 1
    xil_printf("Number of Addresses %d\n\r",size);
#endif
    for(int i=0; i<size; i++){

    	Xil_Out32(reg_block_base_addr + 4*addr[i], val[i]);

    	unsigned int reg_val= Xil_In32(reg_block_base_addr + 4*addr[i]);

#if FPGA_COMMBLOCK_DEBUG == 1
       xil_printf("Write address %d	 Value written %d\n\r", addr[i], reg_val);
#endif
    }
}


unsigned int Read_FIFO_Stream(unsigned int* addr, unsigned int* val, unsigned int size){
	unsigned int tmpStearmAddr = 0;
	unsigned int tmpStreamSize = 0;
#if FPGA_COMMBLOCK_DEBUG == 1
	xil_printf("Number of Addresses %d\n\r",size);
#endif
	for(int i=0; i<size; i++){
		tmpStearmAddr = fifo_stream_F2A_base_addr+addr[i];
		tmpStreamSize = val[i];
#if FPGA_COMMBLOCK_DEBUG == 1
		xil_printf("FIFO Stream Address 0x%x\n\r", tmpStearmAddr);
#endif
//		cur_buf = ( u8* ) FIFO_STREAM_ADDR;
//		HiCCE_DMA_Tranfer_sim(tmpStearmAddr, tmpStreamSize);
		HiCCE_DMA_Tranfer(tmpStearmAddr, tmpStreamSize);

	}
	return tmpStearmAddr;
}

