Hello PDN
Project Description
A hardware platform which can be used to learn first steps (Hello World) into the Power Delivery Network (PDN) measurement and simulation world.
This project describes a PCB with additional connectors to measure the power distribution quality.
Main Features
Block diagram presented below
- Form factor:
- Shall allow for easy access to all components while the board is placed on a table/bench
- Board shall be steady while probes are attached and measurements performed i.e. this probably implies some minimum form factor size
- Optionally could allow to mount the board in a crate/chassis ( uTCA, VME, PCIe card form factor ? )
- Device - Xilinx MPSoC device
- System on Chip with multi-core ARM, multi-core Realt-Time ARM, GPU, and optional video codec (not needed for this study)
- Multiple power rails
- Multiple power domains
- Full power/Low power modes
-
Package C784:
- supporting 10 different devices
- CG, EG and EV models
- Available device sizes from ZU2 (~100k FF/Cells) to ZU5 (~250k FF/Cells)
-
Other packages:
- C1156
- B900
- C900
- Multiple versions of PCB layout supporting C784, B900, and C1156 packages
-
Board management controller
- Texas Instruments MSP430
Pre-layout study using SI/PI/PDN analysis tools
- Optimize capacitor network advised by vendors
- Detect resonances
- Aim for flat impedance profile if possible
PDN VNA measurements
- Easy attachment points for Low frequency VNA
- MPSoC UG583 states to design PDN up to 15/80 MHz - above that the on-chip capacitors will take over
Dynamic current measurements
- PMBUS current and voltage measurements (low sampling rate)
- Oscilloscope with two type of probes (high sampling rate):
- high-dynamic range current probe
- low-ripple/high offset voltage probe
Xilinx MPSoC
- System on Chip with Processor and FPGA sub-systems
- Many different power rails
- Dynamic power management
- Combined with TI MSP430 micro controller allows for complex demonstration scenarios (Xilinx Power Advantage demo)
Power Delivery Network (PDN) based on Infineon chips
- Small footprint with multiple power rails
- Support for MPSoC low power scenarios (-L2 devices, with core voltage of either 0.72 or 0.85 Volts).
- PMBUS
- Architecture can be scaled from EG2 (smallest) to EG19 (biggest) devices. Support of big RFSoC devices for PS, PL and RF subsystems.
Users
- CERN, Switzerland
- Anyone interested to contribute
Project information
Bibliography
- DesignCon proceedings
- VRM point of view: Steve Sandler: Power Integrity: Measuring, Optimizing, and Troubleshooting Power Related Parameters in Electronics Systems
- Chip point of view: Larry D. Smith and Eric Bogatin: Principles of Power Integrity for PDN Design--Simplified: Robust and Cost Effective Design for High Speed Digital Products
- Zynq UltraScale+ MPSoC Product Selection Guide: https://www.xilinx.com/support/documentation/selection-guides/zynq-ultrascale-plus-product-selection-guide.pdf
- Infineon's Complete power supply reference design for Xilinx Kintex, Virtex FPGAs & Zynq SoCs/MPSoCs https://www.infineon.com/cms/en/product/promopages/xilinx-SoC-FPGA-power-reference-design/
Contacts
Design and general questions
Status
Date | Event |
---|---|
11-03-2020 | Adding more information. |
09-07-2018 | First ideas for making this PDN measurement PCB. |
17-08-2018 | Added block diagrams. Added feature list |
9 July 2018