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Add pre-post fetch commands
#32
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 29, 2019
Add support for Synopsys' Synplify
#30
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 30, 2019
Xilinx ISE: make project fails if project file exists
#99
· opened
Sep 11, 2019
by
Dimitris Lampridis
bug
0
updated
Sep 11, 2019
Add an option to display full error log in case of an error
#89
· opened
Apr 29, 2019
by
Nicolas Chevillot
feature
CLOSED
1
0
updated
Jun 03, 2019
--sufix command is a typo => rename to --suffix for proper english
#90
· opened
Apr 30, 2019
by
Nicolas Chevillot
bug
CLOSED
1
0
updated
Jun 03, 2019
VHDL parser: instantiations with archietecture selection
#2
· opened
Mar 21, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
Emit a warning when fetch doesn't points to a specific repository commit or tag
#24
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 30, 2019
VHDL parser: split entity and architecture
#3
· opened
Mar 21, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
support of VHDL, SystemVerilog configuration blocks
#49
· opened
Nov 18, 2014
by
Adrian Fiergolski
feature
CLOSED
1
updated
Oct 31, 2019
circular dependenceis
#52
· opened
Nov 07, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
Test of Active-HDL failes under CMD
#6
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
Hdlmake vsim & xsim targets compile verilog headers as separate files.
#8
· opened
Feb 03, 2018
by
Tomasz Wlostowski
bug
CLOSED
2
updated
Mar 29, 2019
Incorrect source file handling in Diamond (and Libero)
#5
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
multitline signal declaration generates wrong relations in VHDL
#13
· opened
Nov 14, 2016
by
Nicolas Chevillot
bug
0
updated
Feb 12, 2019
modules export tool with lightweight GUI
#18
· opened
Jun 02, 2016
by
Grzegorz Daniluk
feature
CLOSED
2
updated
Mar 31, 2019
Do not fetch submodules recursively
#15
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Wrong version for ISE project in generated .xise files
#41
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Flatten option for Fetch doesn't work
#16
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
VHDL: attributes
#46
· opened
Mar 27, 2015
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
Vivado doesn't support SPEC V4 counter test
#47
· opened
Feb 07, 2015
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
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