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Hdlmake
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Hdlmake
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Hdlmake now depends on the networkx package
#39
· opened
Mar 30, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Add improved granularity to ISE synthesis makefile
#40
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
0
updated
Feb 12, 2019
Wrong version for ISE project in generated .xise files
#41
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Cannot list files from outside a top module
#42
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
0
updated
Feb 12, 2019
Enforced compilation
#43
· opened
Feb 22, 2016
by
Adrian Fiergolski
feature
CLOSED
1
updated
Mar 31, 2019
Hdlmake v2.1 not cleaning fetched modules
#44
· opened
Jan 19, 2016
by
Marco Roda
CLOSED
1
updated
Feb 12, 2019
Have only one call to os.getcwd()
#45
· opened
Oct 13, 2015
by
Nicolas Chevillot
feature
CLOSED
2
updated
Feb 12, 2019
VHDL: attributes
#46
· opened
Mar 27, 2015
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
Vivado doesn't support SPEC V4 counter test
#47
· opened
Feb 07, 2015
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Ugly report messages if synthesis tool not found
#48
· opened
Feb 07, 2015
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
support of VHDL, SystemVerilog configuration blocks
#49
· opened
Nov 18, 2014
by
Adrian Fiergolski
feature
CLOSED
1
updated
Oct 31, 2019
library support
#50
· opened
Nov 10, 2014
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
VHDL: conent of generate
#51
· opened
Nov 07, 2014
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
circular dependenceis
#52
· opened
Nov 07, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
VHDL: case sensitiveness
#53
· opened
Nov 05, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
instantiation without component declaration (VHDL)
#54
· opened
Nov 05, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
libraries used in vhdl files are not added to dependencies
#55
· opened
Nov 05, 2014
by
Adrian Fiergolski
bug
CLOSED
2
updated
Mar 29, 2019
imported packages are not added in dependencies for SystemVerilog files
#56
· opened
Oct 03, 2014
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
no attribute 'parse' for '.vo' files
#57
· opened
Oct 02, 2014
by
Adrian Fiergolski
bug
CLOSED
0
updated
Feb 12, 2019
VHDL parser does not correctly detect and remove character/string literals
#58
· opened
Sep 27, 2014
by
Joshua Smith
bug
CLOSED
1
updated
Feb 12, 2019
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