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Hdlmake
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Test of Active-HDL failes under CMD
#6
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
Active-HDL not working
#7
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
Incorrect source file handling in Diamond (and Libero)
#5
· opened
Mar 14, 2018
by
Jan L.
CLOSED
1
updated
Mar 30, 2019
Add pre-post fetch commands
#32
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 29, 2019
libraries used in vhdl files are not added to dependencies
#55
· opened
Nov 05, 2014
by
Adrian Fiergolski
bug
CLOSED
2
updated
Mar 29, 2019
parser fails to find includes from SV files
#29
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
dependency generation for simulation
#71
· opened
Nov 30, 2012
by
Projects
feature
CLOSED
3
updated
Mar 29, 2019
incl_makefiles being ignored
#1
· opened
Mar 29, 2018
by
Theo Markettos
CLOSED
1
updated
Mar 29, 2019
The parser doesn't work with VHD records
#31
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
Hdlmake vsim & xsim targets compile verilog headers as separate files.
#8
· opened
Feb 03, 2018
by
Tomasz Wlostowski
bug
CLOSED
2
updated
Mar 29, 2019
isim tool and mixed language code
#11
· opened
Jul 17, 2017
by
Karol Krizka
CLOSED
1
updated
Mar 29, 2019
Rare Labeling in Verilig causes Warning of non-existing dependencies
#19
· opened
Jun 02, 2016
by
Andreas Bergmann (Consult)
CLOSED
1
updated
Mar 29, 2019
Support for skipping encoded system verilog files
#22
· opened
May 31, 2016
by
Nicolas Chevillot
feature
CLOSED
2
updated
Mar 29, 2019
Imporve submodules & fetch behavior
#25
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
1
updated
Mar 29, 2019
List-files doesn't generate the parsed dependency-driven fileset
#26
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
2
updated
Mar 29, 2019
Hdlmake includes the target file when generating a simulation Makefile
#27
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
The information about "circular[...] dependency dropped" is neither error nor warning
#28
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
Incorporate way of handling Xilinx Coregen ( *.xco ) components
#65
· opened
Apr 30, 2014
by
David Cussans
CLOSED
3
updated
Mar 29, 2019
XISE: properties from manifest
#64
· opened
May 21, 2014
by
Tom Levens
CLOSED
3
updated
Mar 29, 2019
Add Icarus Verilog support for simulation makefiles
#82
· opened
Jun 20, 2011
by
Paweł Szostek
feature
CLOSED
0
updated
Feb 12, 2019
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