Issues · Projects / Hdlmake · Open Hardware Repository

fetchto variable should be converted to an absolute path

#118 · opened Dec 05, 2022 by Dimitris Lampridis bug
- 0
updated Dec 05, 2022
[Vivado] Source files generated from IP customization files (xci) not included in library 'work'

#112 · opened Jun 29, 2021 by Augusto Fraga Giachero bug
- CLOSED
- 1
updated Jun 30, 2021
Xilinx ISE: make project fails if project file exists

#99 · opened Sep 11, 2019 by Dimitris Lampridis bug
- 0
updated Sep 11, 2019
--sufix command is a typo => rename to --suffix for proper english

#90 · opened Apr 30, 2019 by Nicolas Chevillot bug
- CLOSED
- 1
- 0
updated Jun 03, 2019
VHDL parser: instantiations with archietecture selection

#2 · opened Mar 21, 2018 by Adrian Fiergolski bug
- CLOSED
- 1
updated Feb 12, 2019
VHDL parser: split entity and architecture

#3 · opened Mar 21, 2018 by Adrian Fiergolski bug
- CLOSED
- 1
updated Feb 12, 2019
pip installation

#4 · opened Mar 20, 2018 by Adrian Fiergolski bug
- CLOSED
- 1
updated Mar 30, 2019
Hdlmake vsim & xsim targets compile verilog headers as separate files.

#8 · opened Feb 03, 2018 by Tomasz Wlostowski bug
- CLOSED
- 2
updated Mar 29, 2019
[SV + UVM]: modelsim and +incdir+

#9 · opened Jan 30, 2018 by Adrian Fiergolski bug
- CLOSED
- 2
updated Mar 30, 2019
[SV + UVM]: Could not find a top level file

#10 · opened Jan 26, 2018 by Adrian Fiergolski bug
- CLOSED
- 1
updated Mar 30, 2019
VHDL parser should create relations for package without library

#12 · opened Nov 15, 2016 by Nicolas Chevillot bug
- 1
updated Mar 30, 2019
multitline signal declaration generates wrong relations in VHDL

#13 · opened Nov 14, 2016 by Nicolas Chevillot bug
- 0
updated Feb 12, 2019
Do not fetch submodules recursively

#15 · opened Jul 22, 2016 by Javier D. Garcia-Lasheras bug
- CLOSED
- 1
updated Feb 12, 2019
Flatten option for Fetch doesn't work

#16 · opened Jul 22, 2016 by Javier D. Garcia-Lasheras bug
- CLOSED
- 1
updated Feb 12, 2019
String Element inside $display Verilog function will be misinterpreted as module

#17 · opened Jun 02, 2016 by Andreas Bergmann bug
- 2
updated Mar 30, 2019
Relations missing for VHDL package to be used in system verilog

#20 · opened Jun 01, 2016 by Nicolas Chevillot bug
- 6
updated Feb 12, 2019
Quit upon error should generate an error code different than 0

#21 · opened May 31, 2016 by Nicolas Chevillot bug
- CLOSED
- 1
updated Mar 30, 2019
List-files doesn't generate the parsed dependency-driven fileset

#26 · opened May 29, 2016 by Javier D. Garcia-Lasheras bug
- CLOSED
- 2
updated Mar 29, 2019
Hdlmake includes the target file when generating a simulation Makefile

#27 · opened May 29, 2016 by Javier D. Garcia-Lasheras bug
- CLOSED
- 1
updated Mar 29, 2019
The information about "circular[...] dependency dropped" is neither error nor warning

#28 · opened May 29, 2016 by Javier D. Garcia-Lasheras bug
- CLOSED
- 1
updated Mar 29, 2019

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