Support for skipping encoded system verilog files
Altera IPs generated by Quartus for simulation are usually encoded system verilog files. Using the verilog parser on those files generates a few errors due to unhandled pragmas.
Example of Altera IP generated system verilog encoded file:
=
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "Model Technology",
encrypt_agent_info = "6.6e"
`pragma protect author = "Altera"
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" ,
key_method = "rsa"
`pragma protect key_block encoding = (enctype = "base64", line_length
= 64, bytes = 128)
rwbOoBiMx1AQzznkMTf3FxI/H0tEXLCN3Jo295s22A4yXPP66ezWWYlav+TQjj5U
CKa2B3wB2fFftusQx1a1Pxvx3Kp8dz5YLCfMI++5RgHKxNMeoGK5DIioQk0ZpyGw
iM4bI9eIfwak84Efwji9wFnIxqre4rfyju4SNaAbpf8=
`pragma protect data_block encoding = (enctype = "base64",
line_length = 64, bytes = 32176)
B8urXoJCg7ak9jn8D1TGJRXRojevshG2pfcR1+bFPPof7Pb6p2V8EAs3enmzvLsQ
...
H3T4911b+8lelVwNuUCIrA
`pragma protect end_protected
===
Everything between:
`pragma protect begin_protected
and
`pragma protect end_protected
should be ignored.
The following pragma should be ignored: