isim tool and mixed language code
I am getting the following error when running `make` to compile a testbench for isim.
No rule to make target `work/auto_baud_with_tracking/.auto_baud_with_tracking_vhd', needed by `work/serial_to_wb/.serial_to_wb'. Stop.
My code is using a mix of VHDL (most of the code, including `serial_to_wb` entity) and Verilog (third party serial com module). The `auto_baud_with_tracking` is an entity in the serial com module and hence defined in the makefile under the target `work/auto_baud_with_tracking/.auto_baud_with_tracking_v`.
I've fixed this by editing hdlmake/tools/isim.py on line 258 to get the extension from the dependency (dep_file) instead of the parent (vhdl_file). Is this the right thing to do? The full patch is attached.