Hdlmake issueshttps://ohwr.org/project/hdl-make/issues2019-06-03T06:47:11Zhttps://ohwr.org/project/hdl-make/issues/89Add an option to display full error log in case of an error2019-06-03T06:47:11ZNicolas ChevillotAdd an option to display full error log in case of an errorIn order to be able to debug the hdl-make code, it is interesting to have the full traceback instead of only the reported error (exception)Nicolas ChevillotNicolas Chevillothttps://ohwr.org/project/hdl-make/issues/88Don't include Verilog include files in Quartus project2019-04-04T05:29:39ZTom LevensDon't include Verilog include files in Quartus projectVerilog include files should not be included in the file list in the Quartus project, otherwise Quartus tries to parse them as regular Verilog files (which may not be valid).https://ohwr.org/project/hdl-make/issues/87SystemVerilog includes2019-04-04T18:19:29ZTom LevensSystemVerilog includesIn #83, Javier found the following errors from Quartus, and these are related to using _SystemVerilog_ code on a _Verilog_ file:
```
Error (10839): Verilog HDL error at VadjConfig.vh(13): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 13
Error (10839): Verilog HDL error at VadjConfig.vh(17): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 17
Error (10839): Verilog HDL error at VadjConfig.vh(18): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 18
Error (10839): Verilog HDL error at VadjConfig.vh(19): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 19
Error (10839): Verilog HDL error at VadjConfig.vh(20): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 20
Error (10839): Verilog HDL error at VadjConfig.vh(21): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 21
Error (10839): Verilog HDL error at VadjConfig.vh(22): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 22
Error (10839): Verilog HDL error at VadjConfig.vh(23): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 23
Error (10839): Verilog HDL error at VadjConfig.vh(24): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 24
Error (10839): Verilog HDL error at VadjConfig.vh(25): declaring global objects is a SystemVerilog feature File: /home/jgarcia/Workspace/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VadjConfig.vh Line: 25
```
Should this header file not be considered a SV file if it is included from a SV source?https://ohwr.org/project/hdl-make/issues/86No expansion for macro2019-04-02T13:31:40ZTom LevensNo expansion for macroTriggered by #83, I see the following error even though the macro is defined in an include file.
```
ERROR vlog_parser.py:271: do_expand() No expansion for macro '`SYS_CLK_FREQ' (localparam c_ClkFrequency = `SYS_CLK_FREQ;) (/afs/cern.ch/work/t/tlevens/repos/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VfcHdSystem.sv)
```https://ohwr.org/project/hdl-make/issues/85SystemVerilog files included twice in Quartus project2019-04-02T12:10:19ZTom LevensSystemVerilog files included twice in Quartus projecthdlmake seems to include the SystemVerilog files twice in my Quartus project, once as a `SYSTEMVERILOG_FILE` and then later as a `VERILOG_FILE`.
Quartus seems to take the latter definition and complains that they use invalid syntax.
Here is a snip of the files.tcl script:
```
...
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/AddrDecoderWbSys.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpMaster.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpReqArbiter.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/InterruptManagerWb.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/OneWireBus.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpIdReader.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpStatusRegs.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SpiMaster.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SysAppIdRegs.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/UniqueIdTemp.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VadjControl.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcConfiguration.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdSystem.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdTop.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VoltageMonitoring.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/AddrDecoderWbSys.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpMaster.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpReqArbiter.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/InterruptManagerWb.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/OneWireBus.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpIdReader.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpStatusRegs.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SpiMaster.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SysAppIdRegs.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/UniqueIdTemp.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VadjConfig.vh -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VadjControl.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcConfiguration.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdSystem.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdTop.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdUserIo_unused.vh -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdUserIo.vh -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VoltageMonitoring.sv -library work
...
```https://ohwr.org/project/hdl-make/issues/84Quartus SEARCH_PATH from include_dirs2019-04-02T13:26:02ZTom LevensQuartus SEARCH_PATH from include_dirsItems in the `include_dirs` directive should generate a Quartus `SEARCH_PATH` entry:
For example:
```
include_dirs = ['../mydir_a', '../mydir_b']
```
Should result in:
```
set_global_assignment -name SEARCH_PATH ../mydir_a
set_global_assignment -name SEARCH_PATH ../mydir_b
```https://ohwr.org/project/hdl-make/issues/83include_dirs does not seem to work for synthesis2019-04-02T09:43:21ZTom Levensinclude_dirs does not seem to work for synthesisI have [SystemVerilog project](https://gitlab.cern.ch/bi/BCT/BTrain-VFCHD-DCCT-FMC) that uses an include to define some constants. Due to the BI VFC project structure, the include file is not in the same directory as the top level source.
I have added the `include_dirs = ["../modules"]` directive to my Manifest.py, but I still get the following errors:
```
INFO action.py:169: build_file_set() Detected 7 supported files that are not parseable
INFO action.py:172: build_file_set() Detected 347 supported files that can be parsed
ERROR vlog_parser.py:270: do_expand() No expansion for macro '`SYS_CLK_FREQ' (localparam c_ClkFrequency = `SYS_CLK_FREQ;) (/afs/cern.ch/work/t/tlevens/repos/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VfcHdSystem.sv)
ERROR vlog_parser.py:123: _search_include() Can't find VfcHdConfig.vh for /afs/cern.ch/work/t/tlevens/repos/BTrain-VFCHD-DCCT-FMC/libs/VFC-HD_System/hdl/modules/VfcHdTop.sv in any of the include directories: ../../libs/VFC-HD_System/hdl/modules
Exiting
```
It looks like the `include_dirs` is not being taken into account when parsing the files.https://ohwr.org/project/hdl-make/issues/82Add Icarus Verilog support for simulation makefiles2019-02-12T09:35:29ZPaweł SzostekAdd Icarus Verilog support for simulation makefilesAdd iverilog as one of the tools that makefiles are generated for.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/81Finish gdhl support in simulation makefiles2019-02-12T09:35:28ZPaweł SzostekFinish gdhl support in simulation makefilesThe correspondent work is put in ghdl branchJavier D. Garcia-LasherasJavier D. Garcia-Lasherashttps://ohwr.org/project/hdl-make/issues/80Finish quartus support2019-02-12T09:35:28ZPaweł SzostekFinish quartus supportThe correspondent work is present in quartus branchPaweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/79Add more logic into ise version detection2019-02-12T09:35:27ZPaweł SzostekAdd more logic into ise version detectionThe appropriate ISE path can be found using 'which' command. With
'which' one can find path to used binaries. When going up in the
directory structure, there is a chance that you will reach a directory,
whose name indicates the version.
The same must be done in remote synthesis (which involves developing
some in-line makefile script).Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/78python version2019-02-12T09:35:27ZAlessandro Rubinipython versionI've an older debian, with python 2.5
hdlmake is not working and spits an unphatomable error.
The problem is that zipfile autodecompression was introduced
in version 2.6, and when you run "make" to build hdlmake itself
(the zip file) the version is not checked.
Maybe it should be checked, although I'm aware most people doesn't
use old tools.https://ohwr.org/project/hdl-make/issues/77hdlmake --ise-proj2019-02-12T09:35:26ZCesar Pradoshdlmake --ise-projhdlmake --ise-proj fails because it is not able to determine the version
of xst. You're trying to get the version from the insatllation folder,
at least in the last installations of ise I don't have any more the
version in the path and I think that it is not the best solution. I
couldn't find a neat way of getting the version of xst, but at least I
can get by with this:
$xst --help
Release 13.2 .....
I have modified the source code where you're looking for the soft
version with $which xst and it is working, if you find a better way,
better, if not I would rely on the installation path.https://ohwr.org/project/hdl-make/issues/76typo in help message2019-02-12T09:35:26ZProjectstypo in help messageThe description for --list-files says "List all files in a from of a
space-separated string".
Should be form instead of from -\> "List all files in a form of a
space-separated string".Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/75fetch tag/commit2019-02-12T09:35:25ZProjectsfetch tag/commitAdd the ability to fetch a particular git tag or commit for a module.
\-\> With a special synthesis in the Manifest file.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/74Add possibility to pass user defined variables2019-02-12T09:35:25ZProjectsAdd possibility to pass user defined variablesAdd possibility to pass user defined variables from the root Manifest to
the others Manifests.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/73Fix a bug in dependency generation2019-02-12T09:35:24ZPaweł SzostekFix a bug in dependency generationVamsi Vytla:
In file 'dep\_solver.py': f.\_dep\_fixed is set when
get/set\_dep\_requires/provides are invoked. Suppose, the variable
'\_dep\_fixed' for 'file\_2.v' gets set in the invocation of
'\_*create\_deps()' during the call '*\_lookup\_post\_provider()' for
'file\_1.v', then the solver never gets a chance to set the post
provider for 'file\_2.v' before 'file\_2.v' in the fset.Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/72Add "Create Binary Configuration File" option by default when creating xise p...2019-02-12T09:35:24ZProjectsAdd "Create Binary Configuration File" option by default when creating xise project file.By default, when creating the xise project file, the option to generate
a .bin file should be
activated.
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>Paweł SzostekPaweł Szostekhttps://ohwr.org/project/hdl-make/issues/71dependency generation for simulation2019-03-29T22:51:53ZProjectsdependency generation for simulationdependencies are badly generated for simulation (branch master)
but on branch isyp they are properly generated\!Javier D. Garcia-LasherasJavier D. Garcia-Lasherashttps://ohwr.org/project/hdl-make/issues/70Add vhd file generation during build2019-02-12T09:35:22ZProjectsAdd vhd file generation during buildEvery time a bitstream is build, a vhd file should be created.
This vhd file can be used to embed information to the bitstream.
The file should contain (to be discussed):
\> 1. Synthesis tool name+version
\> 2. Git top-module name+url
\> 3. Full git hash of the top-module
\> 4. Name of the person synthesizing (unix id)
\> 5. Date of the the synthesis
The idea is to be able to read this information from outside the FPGA to
uniquely identify a bitstream.Paweł SzostekPaweł Szostek