Programming languages used in this repository
-
Python
92.08 %
-
VHDL
4.16 %
-
Verilog
2.77 %
-
Makefile
0.41 %
-
Tcl
0.4 %
-
SystemVerilog
0.09 %
-
Stata
0.06 %
-
Coq
0.02 %
Commit statistics for 9732b71939696206eb1a00a9261ae8477aa4aa7a Jan 12 - Nov 01
- Total: 1332 commits
- Average per day: 0.4 commits
- Authors: 24
Commits per day of month
Commits per weekday
Commits per day hour (UTC)