Commits · a90100a12b44b9bcb8324e98fbd411bc8c3ff77c · Projects / Hdlmake · Open Hardware Repository

09 Aug, 2016 1 commit
- First tests for integrating Vivado Simulator · a90100a1
  Javier D. Garcia-Lasheras authored Aug 09, 2016
  
  a90100a1
02 Aug, 2016 1 commit
- Add the -g2012 option to the VHDL demo for IVerilog · 2aee04b8
  Javier D. Garcia-Lasheras authored Aug 02, 2016
  
  2aee04b8
23 Jul, 2016 1 commit
- Fix VHDL test for Quartus, missing module path · 70cd68c0
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  70cd68c0
22 Jul, 2016 1 commit
- Add sim_top variable to complement syn_top: top_module is redundant now · 5aa91926
  Javier D. Garcia-Lasheras authored Jul 22, 2016
  
  5aa91926
28 Mar, 2015 1 commit
- Added Aldec Riviera support for simulation. · 8bd44158
  Josh Smith authored Mar 28, 2015
  
  8bd44158
08 Feb, 2015 1 commit
- Vivado cannot be used with an Spartan6 device: remove SPEC v4 Vivado test · 427aa7bd
  Garcia-Lasheras authored Feb 08, 2015
  
  427aa7bd
07 Feb, 2015 2 commits
- Add IVerilog VHDL based counter test · e8d09edb
  Garcia-Lasheras authored Feb 07, 2015
  
  e8d09edb
- Add test counter example for Vivado · 32db68e1
  Garcia-Lasheras authored Feb 07, 2015
  
  32db68e1
10 Oct, 2014 1 commit
- Disable optimisations in order to have visibility of counter's signal. · aabe6c84
  Adrian Fiergolski authored Oct 10, 2014
  
  aabe6c84
16 Sep, 2014 1 commit
- Simple 8-bit counter test for syn/sim, VHDL/Verilog · cc56877a
  garcialasheras authored Sep 16, 2014
  
  cc56877a