Commits · 75dbfdde359ba138b8487c9bac8dcf27568ee1ad · Projects / Hdlmake · Open Hardware Repository

26 Jul, 2019 1 commit
- tests/counter/sim/ghdl: use && instead of ; to chain commands. · 7ab409c2
  Tristan Gingold authored Jul 26, 2019
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By Hackathlete.
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  7ab409c2
30 Mar, 2019 2 commits
- Fix and upgrade the counter test demo HDL files · c97cff89
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  c97cff89
- Test of Active-HDL failes under CMD · 302aab7d
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  302aab7d
26 May, 2017 1 commit
- Add a demo test for Xilinx Vivado synthesis on a Zedboard platform · 858f517b
  Javier D. Garcia-Lasheras authored May 26, 2017
  
  858f517b
25 May, 2017 1 commit
- Split Vivado into two different tool modules for synthesis and simulation · f5fd4714
  Javier D. Garcia-Lasheras authored May 25, 2017
  
  f5fd4714
13 Mar, 2017 2 commits
- Handle hdl as a dictionay in Aldec Active-HDL · 5c7c8e07
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  5c7c8e07
- Add a new Verilog test for Vivado simulation · d983c430
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  d983c430
10 Mar, 2017 3 commits
- Use generics in VHDL counter test to select sim and syn dividers · 03047436
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  03047436
- Update the VHDL counter test · 7feedf4d
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  7feedf4d
- Update Verilog counter test: counter + shifter · feff4994
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  feff4994
09 Mar, 2017 1 commit
- Add the counter test for IceStorm synthesis · 1879e826
  Javier D. Garcia-Lasheras authored Mar 09, 2017
  
  1879e826
09 Aug, 2016 1 commit
- First tests for integrating Vivado Simulator · a90100a1
  Javier D. Garcia-Lasheras authored Aug 09, 2016
  
  a90100a1
02 Aug, 2016 1 commit
- Add the -g2012 option to the VHDL demo for IVerilog · 2aee04b8
  Javier D. Garcia-Lasheras authored Aug 02, 2016
  
  2aee04b8
23 Jul, 2016 1 commit
- Fix VHDL test for Quartus, missing module path · 70cd68c0
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  70cd68c0
22 Jul, 2016 1 commit
- Add sim_top variable to complement syn_top: top_module is redundant now · 5aa91926
  Javier D. Garcia-Lasheras authored Jul 22, 2016
  
  5aa91926
28 Mar, 2015 1 commit
- Added Aldec Riviera support for simulation. · 8bd44158
  Josh Smith authored Mar 28, 2015
  
  8bd44158
08 Feb, 2015 1 commit
- Vivado cannot be used with an Spartan6 device: remove SPEC v4 Vivado test · 427aa7bd
  Garcia-Lasheras authored Feb 08, 2015
  
  427aa7bd
07 Feb, 2015 2 commits
- Add IVerilog VHDL based counter test · e8d09edb
  Garcia-Lasheras authored Feb 07, 2015
  
  e8d09edb
- Add test counter example for Vivado · 32db68e1
  Garcia-Lasheras authored Feb 07, 2015
  
  32db68e1
10 Oct, 2014 1 commit
- Disable optimisations in order to have visibility of counter's signal. · aabe6c84
  Adrian Fiergolski authored Oct 10, 2014
  
  aabe6c84
16 Sep, 2014 1 commit
- Simple 8-bit counter test for syn/sim, VHDL/Verilog · cc56877a
  garcialasheras authored Sep 16, 2014
  
  cc56877a