Hdlmake:3.2 commitshttps://ohwr.org/project/hdl-make/commits/3.22019-04-11T08:32:01Zhttps://ohwr.org/project/hdl-make/commit/c4b5fcedfde2114caf4417a86712163252d3b7bdBump version to 3.22019-04-11T08:32:01ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/54db676499a6fc7bcf8484ef99dd2d66527e46d7Update docs with the new Quartus property dictionary format2019-04-11T08:09:42ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/e56bcca8a0dfc77a52db17621e225b4a74b8525dFix for issue #35, improve ifdef matching in Verilog parser2019-04-09T10:30:51ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/edb220cbd1cfa0e69cd7f532face54fb1acda53cProvide the Quartus properties as a dictionary2019-04-04T13:08:54ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/63139ec6c5fc907bcfac9715562eb1b501e0925dEscape quotations in the Quartus Makefile user properties2019-04-04T07:05:34ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/71b60ddede420f7605f1bd84e633d3ce23358fb5Do not try to synthesize Verilog and SystemVerilog includes2019-04-03T23:02:26ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/a348e326466a0810478383fc69842b36b7698405Do not enable SystemVerilog 2005 in Quartus, but support syn_properties in th...2019-04-03T21:38:44ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/2f5ab5375eb32bd19962ed818d533f813ad6f02bEnable SystemVerilog 2005 as default Verilog input version in Quartus2019-04-02T10:15:31ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/49cc92e60d40e0bd2e20fe4d97ef8689d432c05dAdd include_dirs as SEARCH_PATH in Quartus2019-04-02T09:55:01ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/6bda472d3f3c2f522a583f163ffe93b8f17a9ef0Fix System Verilog files included on Verilog synthesis list2019-04-02T09:35:30ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/ba831ab5076632961eb6b6f1d1886085975dbfe3Hot Fix include_dirs mechanism2019-04-01T22:26:36ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/ffa3ba6c7caf8e74fe9290d0bb47cda389e8f0d8Bump version to 3.12019-03-30T15:26:36ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/ecef800f6a7b3653a3689afcf98bfe78f2c87ab0Fix typo in Xilinx ISim at the supported tools table in docs2019-03-30T15:13:56ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/e826f6e11d3f9a0895bb2067464ae5a52b47bbd5Fix missing makefile command in the prefix and sufix examples2019-03-30T15:09:20ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/c97cff89f4b08f9b5e8d722ccb6494176ff88247Fix and upgrade the counter test demo HDL files2019-03-30T14:56:35ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/1627ac83f6ccabaefcf9fac40f05e4806c6bf527Improve how new_dep_solver handles a missing top_module definition2019-03-30T04:39:01ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/b3a15d2da433f41186774ee32039175df068e841Adjust links in the documents to the new GitLab management2019-03-30T03:45:57ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/d8233b711b1110d5d2aa8d4f5b74e0a99c9e3bb2Quit upon error should generate an error code different than 02019-03-30T02:56:26ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/4c8d351cd0a2033b6099d9672777cb8312329cc1Include a note in the docs about Modelsim +incdir+ management2019-03-30T01:33:43ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/302aab7dc159dc182a7e31efbebc9e9ab9dc801cTest of Active-HDL failes under CMD2019-03-30T00:54:39ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/2431e3874150ddf38a6fba8feff4d7493ca29267Fix Active-HDL support in Windows Cmd and PowerShell2019-03-30T00:50:24ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/13f5d20ee8d3cd8077a350b71f5a04d7cfd77edeFix file source handling in Diamond and Libero2019-03-30T00:43:09ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/7959a8deabd98258bba3a4d6b8f934f1448f9102More helpful error message when no action set causing tool not to be set.2019-03-29T23:12:00ZWill Kampwillkamp@gmail.comhttps://ohwr.org/project/hdl-make/commit/033590e18cf27a8513928846321fb25e6ababc40Better support multiple VHDL libraries.2019-03-29T23:11:00ZWill Kampwillkamp@gmail.com
VHDL_parser.py extracts the library from instantiations.
new_dep_solver.py does not assume the work library.
core.py inherits the library from the parent Manifest.
https://ohwr.org/project/hdl-make/commit/26f08930699c2bcf4ba95bacbdc74b979b1cabc5Fix incl_makefiles being ignored at synthesis and simulation2019-03-29T22:02:02ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/4043e15bc82674be2c7721a64a0f21cec6015d68Fix ISIM support for mixed HDL languages2019-03-29T18:47:54ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/d3824c98f324d7e5a1c7ede226113148ed683ce5XCO files should be handled by ISE, not only by Vivado and PlanAhead.2019-03-29T17:18:42ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/bc1e679605f718bbfa3c8599715bb4890f1f7501Fix project links in the docs to match the new OHWR.org site features2018-12-21T20:05:33ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/cd664d09a2943b63c2d4426e4b54ca8dec725636Report an error and quit when the manifest file is not found2018-12-21T19:51:58ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/b112db0d26f19d2a306906ca44b76e50e9751391Fix and document Xilinx Vivado and PlanAhead project language selection2018-12-21T19:34:54ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/530d2f14910cef3dc9f0747aacab8481b9fc7584Include the Xilinx BMM files in Vivado, ISE and PlanAhead2018-12-21T18:40:54ZJavier Garciajgarcia@gl-research.comhttps://ohwr.org/project/hdl-make/commit/968fa87d38fb65ad56dbc7e3e2131a89c0635e88Document and effectively support ghdl_opt setting.2018-11-30T09:27:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/hdl-make/commit/f38d03cdbc05cf03b42ed12512fce6e5fa6e07bbFix bug 1761: VHDL instantiations with archietecture selection2018-03-21T12:17:32ZAdrian Fiergolskiadrian.fiergolski@cern.chhttps://ohwr.org/project/hdl-make/commit/1a5fc8eeed54f4beb2af4365eb16522cf1a42a8aFix bug 1760: entity and architecture declaration in mutiple files.2018-03-21T10:22:16ZAdrian Fiergolskiadrian.fiergolski@cern.chhttps://ohwr.org/project/hdl-make/commit/db4e1ab6456ce6b949b166da3afb953b25d4eb4aPrevent tool from compiling (system)verilog included files.2018-03-07T14:37:57ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/hdl-make/commit/943c08c5c3c9847680144574a345c1f33000e77cMake "none" the default top_module if not specified in Manifest.2018-02-19T23:20:52ZWill Kampwkamp@aut.ac.nzhttps://ohwr.org/project/hdl-make/commit/01411df9874084d8197c1cbc31cd5fd80aacb0ecWhen listing files use top_module from the Manifest, overwite with --top argu...2018-02-12T05:14:13ZWill Kampwkamp@aut.ac.nzhttps://ohwr.org/project/hdl-make/commit/e8c1f12ca59ee01e617a1de248cd9f5e3390760dRecognise entire VHDL functions and entity instanciations as instances. 2018-02-12T04:22:15ZWill Kampwkamp@aut.ac.nz
Gobble entire VHDL function to avoid input parameters being recognised as instances.
Entity instanciations recognised as instances as well - borrowed from rjen's commit <a href="/project/hdl-make/commit/d0ba0268fc1d9303380daa2b386c046d0634b933" data-original="d0ba0268fc1d9303380daa2b386c046d0634b933" data-link="false" data-link-reference="false" data-project="10721" data-commit="d0ba0268fc1d9303380daa2b386c046d0634b933" data-reference-type="commit" data-container="body" data-placement="bottom" title="Modified: - instance regex supports entity instantiation" class="gfm gfm-commit has-tooltip">d0ba0268</a> on feat_svn_ise branch.https://ohwr.org/project/hdl-make/commit/40d233693aa6063b9a88bc8428c95431a281d777Fix sufix code, append to sufix code rather than prefix code.2018-02-12T04:14:36ZWill Kampwkamp@aut.ac.nzhttps://ohwr.org/project/hdl-make/commit/d0d037d3c0db263f76b433180f460a069db962a5SystemVerilog and Verilog file descriptions looked to be flipped in quartus.py2017-09-29T15:40:52ZJoshua A. Einstein-Curtisjeinstei@fnal.gov