Update Verilog counter test: counter + shifter

parent 1879e826
...@@ -10,6 +10,9 @@ module counter ( ...@@ -10,6 +10,9 @@ module counter (
Q Q
); );
//--------- Cycles per second -------------------------
parameter cycles_per_second = 12000000;
//--------- Output Ports ------------------------------ //--------- Output Ports ------------------------------
output [7:0] Q; output [7:0] Q;
...@@ -17,14 +20,30 @@ module counter ( ...@@ -17,14 +20,30 @@ module counter (
input clock, clear, count; input clock, clear, count;
//--------- Internal Variables ------------------------ //--------- Internal Variables ------------------------
reg ready = 0;
reg [23:0] divider;
reg [7:0] Q; reg [7:0] Q;
//--------- Code Starts Here -------------------------- //--------- Code Starts Here --------------------------
always @(posedge clock)
if (clear) begin always @(posedge clock) begin
Q <= 8'b0 ; if (ready)
end else if (count) begin begin
Q <= Q + 1; if (divider == cycles_per_second)
end begin
divider <= 0;
Q <= {Q[6:0], Q[7]};
end
else
divider <= divider + 1;
end
else
begin
ready <= 1;
Q <= 8'b00010001;
divider <= 0;
end
end
endmodule endmodule
...@@ -8,6 +8,8 @@ module counter_tb(); ...@@ -8,6 +8,8 @@ module counter_tb();
reg clock, clear, count; reg clock, clear, count;
wire [7:0] Q; wire [7:0] Q;
defparam U_counter.cycles_per_second = 500;
// Initialize all variables // Initialize all variables
initial begin initial begin
$dumpfile("counter_tb.vcd"); $dumpfile("counter_tb.vcd");
...@@ -21,13 +23,13 @@ initial begin ...@@ -21,13 +23,13 @@ initial begin
#5 clear = 1; // Assert the clear signal #5 clear = 1; // Assert the clear signal
#10 clear = 0; // De-assert clear signal #10 clear = 0; // De-assert clear signal
#10 count = 1; // Start count #10 count = 1; // Start count
#2000 count = 0; // De-assert count enable #10000 count = 0; // De-assert count enable
#5 $finish; // Terminate simulation #5 $finish; // Terminate simulation
end end
// Clock generator // Clock generator
always begin always begin
#5 clock = ~clock; // Toggle clock every 5 ticks #1 clock = ~clock; // Toggle clock every 5 ticks
end end
// Connect DUT to test bench // Connect DUT to test bench
......
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