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Commit fe792042 authored by Paweł Szostek's avatar Paweł Szostek
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Add include_dirs variable to manifests 

In this patch a new feature was implemented. It
is now possible to specify include_dirs which
 indicates where to look for includes for
(at least for the time being) Verilog and SV
files. This works as -I option in gcc.
parent 42b4ec49
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Showing with 40 additions and 11 deletions
hdlmake
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src/helper_classes.py
View file @ fe792042
......@@ -56,6 +56,10 @@ class ManifestParser(ConfigParser):
self.add_option('syn_top', default=None, help = "Top level module for synthesis", type = '');
self.add_option('syn_project', default=None, help = "Project file (.xise, .ise, .qpf)", type = '');
self.add_delimiter()
self.add_option('include_dirs', default=None, help="Include dirs for Verilog sources", type = [])
self.add_type('include_dirs', type = "")
self.add_delimiter()
self.add_option('vsim_opt', default="", help="Additional options for vsim", type='')
self.add_option('vcom_opt', default="", help="Additional options for vcom", type='')
......
src/makefile_writer.py
View file @ fe792042
......@@ -325,7 +325,10 @@ clean:
self.write(" $(VLOG_FLAGS) ")
if isinstance(vl, SVFile):
self.write(" -sv ")
self.write("+incdir+"+rp(vl.dirname)+" ")
incdir = "+incdir+"
incdir += '+'.join(vl.include_dirs)
incdir += " "
self.write(incdir)
self.writeln(vl.vlog_opt+" $<")
self.write("\t\t@mkdir -p $(dir $@)")
self.writeln(" && touch $@ \n\n")
......
src/module.py
View file @ fe792042
......@@ -53,6 +53,7 @@ class Module(object):
self.source = source
self.parent = parent
self.isparsed = False
self.include_dirs = None
self.library = "work"
self.local = []
self.git = []
......@@ -217,6 +218,19 @@ class Module(object):
# self.vmap_opt = global_mod.top_module.vmap_opt
self.library = opt_map["library"]
self.include_dirs = []
if opt_map["include_dirs"] != None:
if isinstance(opt_map["include_dirs"], basestring):
self.include_dirs.append(opt_map["include_dirs"])
else:
self.include_dirs.extend(opt_map["include_dirs"])
for dir in self.include_dirs:
if path_mod.is_abs_path(dir):
p.warning(self.path + " contains absolute path to an include directory: " +
dir)
if not os.path.exists(dir):
p.warning(self.path + " has an unexisting include directory: " + dir)
if opt_map["files"] == []:
self.files = SourceFileSet()
......@@ -235,7 +249,7 @@ class Module(object):
quit()
from srcfile import VerilogFile, VHDLFile
self.files = self.__create_flat_file_list(paths=paths);
self.files = self.__create_file_list_from_paths(paths=paths);
for f in self.files:
if isinstance(f, VerilogFile):
f.vsim_opt = self.vsim_opt
......@@ -318,7 +332,7 @@ class Module(object):
return modules
def __create_flat_file_list(self, paths):
def __create_file_list_from_paths(self, paths):
sff = SourceFileFactory()
srcs = SourceFileSet()
for p in paths:
......@@ -327,9 +341,9 @@ class Module(object):
for f_dir in dir:
f_dir = os.path.join(self.path, p, f_dir)
if not os.path.isdir(f_dir):
srcs.add(sff.new(f_dir, self.library, self.vcom_opt, self.vlog_opt))
srcs.add(sff.new(f_dir, self.library, self.vcom_opt, self.vlog_opt, self.include_dirs))
else:
srcs.add(sff.new(p, self.library, self.vcom_opt, self.vlog_opt))
srcs.add(sff.new(p, self.library, self.vcom_opt, self.vlog_opt, self.include_dirs))
return srcs
def build_global_file_list(self):
......
src/msg.py
View file @ fe792042
......@@ -34,6 +34,9 @@ def printhr():
def rawprint(msg = ""):
print(msg)
def warning(msg):
rawprint("WARNING: " + msg)
def echo(msg):
global t0
print(("["+os.path.basename(sys.argv[0]) + " " + "%.5f" % (time.time()-t0) + "]: " + str(msg)))
......
src/srcfile.py
View file @ fe792042
......@@ -23,6 +23,7 @@ import os
import msg as p
import global_mod
import flow
import path as path_mod
class File(object):
def __init__(self, path):
......@@ -204,7 +205,7 @@ class VHDLFile(SourceFile):
return ret
class VerilogFile(SourceFile):
def __init__(self, path, library = None, vlog_opt = None):
def __init__(self, path, library = None, vlog_opt = None, include_dirs = None):
if not library:
library = "work"
SourceFile.__init__(self, path, library);
......@@ -213,6 +214,10 @@ class VerilogFile(SourceFile):
self.vlog_opt = ""
else:
self.vlog_opt = vlog_opt
self.include_dirs = []
if include_dirs:
self.include_dirs.extend(include_dirs)
self.include_dirs.append(path_mod.relpath(self.dirname))
def __create_deps(self):
self.dep_requires = self.__search_includes()
......@@ -236,8 +241,8 @@ class VerilogFile(SourceFile):
return ret
class SVFile(VerilogFile):
def __init__(self, path, library = None, vlog_opt = None):
VerilogFile.__init__(self, path, library, vlog_opt)
def __init__(self, path, library = None, vlog_opt = None, include_dirs = None):
VerilogFile.__init__(self, path, library, vlog_opt, include_dirs)
class UCFFile(File):
def __init__(self, path):
......@@ -317,7 +322,7 @@ class SourceFileSet(list):
return ret
class SourceFileFactory:
def new (self, path, library=None, vcom_opt=None, vlog_opt=None):
def new (self, path, library=None, vcom_opt=None, vlog_opt=None, include_dirs=None):
if path == None or path == "":
raise RuntimeError("Expected a file path, got: "+str(path))
if not os.path.isabs(path):
......@@ -330,9 +335,9 @@ class SourceFileFactory:
if extension == 'vhd' or extension == 'vhdl' or extension == 'vho':
nf = VHDLFile(path, library, vcom_opt)
elif extension == 'v' or extension == 'vh' or extension == 'vo':
nf = VerilogFile(path, library, vlog_opt)
nf = VerilogFile(path, library, vlog_opt, include_dirs)
elif extension == 'sv':
nf = SVFile(path, library, vlog_opt)
nf = SVFile(path, library, vlog_opt, include_dirs)
elif extension == 'ngc':
nf = NGCFile(path)
elif extension == 'ucf':
......
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