Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
fd317f47
Commit
fd317f47
authored
Sep 17, 2019
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Add verilog ifdef/elsif/else test-case
parent
7ab409c2
Hide whitespace changes
Inline
Side-by-side
Showing
7 changed files
with
94 additions
and
0 deletions
+94
-0
Makefile.ref
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
+66
-0
Manifest.py
testsuite/081vlog_ifdef_elsif_else/Manifest.py
+7
-0
mod_a.v
testsuite/081vlog_ifdef_elsif_else/mod_a.v
+2
-0
mod_b.v
testsuite/081vlog_ifdef_elsif_else/mod_b.v
+2
-0
mod_c.v
testsuite/081vlog_ifdef_elsif_else/mod_c.v
+2
-0
vlog.v
testsuite/081vlog_ifdef_elsif_else/vlog.v
+12
-0
test_all.py
testsuite/test_all.py
+3
-0
No files found.
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
0 → 100644
View file @
fd317f47
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VMAP_FLAGS
:=
-modelsimini
modelsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
mod_a.v
\
vlog.v
\
VERILOG_OBJ
:=
work/mod_a/.mod_a_v
\
work/vlog/.vlog_v
\
VHDL_SRC
:=
VHDL_OBJ
:=
INCLUDE_DIRS
:=
LIBS
:=
work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
work/mod_a/.mod_a_v
:
mod_a.v
vlog
-work
work
$(VLOG_FLAGS)
${
INCLUDE_DIRS
}
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/vlog/.vlog_v
:
vlog.v
\
work/mod_a/.mod_a_v
vlog
-work
work
$(VLOG_FLAGS)
${
INCLUDE_DIRS
}
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
sim_post_cmd
:
CLEAN_TARGETS
:=
$(LIBS)
modelsim.ini transcript
clean
:
rm
-rf
$(CLEAN_TARGETS)
mrproper
:
clean
rm
-rf
*
.vcd
*
.wlf
.PHONY
:
mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/081vlog_ifdef_elsif_else/Manifest.py
0 → 100644
View file @
fd317f47
action
=
"simulation"
sim_tool
=
"modelsim"
top_module
=
"gate"
files
=
[
"vlog.v"
,
"mod_a.v"
,
"mod_b.v"
,
"mod_c.v"
]
testsuite/081vlog_ifdef_elsif_else/mod_a.v
0 → 100644
View file @
fd317f47
module
mod_a
()
;
endmodule
testsuite/081vlog_ifdef_elsif_else/mod_b.v
0 → 100644
View file @
fd317f47
module
mod_b
()
;
endmodule
testsuite/081vlog_ifdef_elsif_else/mod_c.v
0 → 100644
View file @
fd317f47
module
mod_c
()
;
endmodule
testsuite/081vlog_ifdef_elsif_else/vlog.v
0 → 100644
View file @
fd317f47
`define
DEF_A
module
gate
;
// My comment
`ifdef
DEF_A
mod_a
mod_a
()
;
`elsif
DEF_B
mod_b
mod_b
()
;
`else
mod_c
mod_c
()
;
`endif
endmodule
testsuite/test_all.py
View file @
fd317f47
...
...
@@ -382,6 +382,9 @@ def test_err_vlog_recursion():
with
pytest
.
raises
(
SystemExit
)
as
_
:
run
([],
path
=
"080err_vlg_recursion"
)
def
test_vlog_ifdef_elsif_else_081
():
run_compare
(
path
=
"081vlog_ifdef_elsif_else"
)
def
test_dep_level
():
run
([
'list-files'
],
path
=
"053vlog_dep_level"
)
run
([
'list-files'
,
'--delimiter'
,
','
],
path
=
"053vlog_dep_level"
)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment