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Hdlmake
Commit fad48533 authored by Tristan Gingold's avatar Tristan Gingold
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tools: minor refactoring (pass top manifest to write_makefile).

parent 25ad26d0
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Showing with 14 additions and 18 deletions
hdlmake/action/commands.py
View file @ fad48533
......@@ -72,7 +72,7 @@ class Commands(Action):
self.solve_file_set()
combined_fileset = self.parseable_fileset
combined_fileset.add(self.privative_fileset)
self.tool.write_makefile(self.top_manifest.manifest_dict,
self.tool.write_makefile(self.top_manifest,
combined_fileset,
filename=filename)
......
hdlmake/tools/makefile.py
View file @ fad48533
......@@ -65,9 +65,9 @@ class ToolMakefile(object):
"""Get the privative format file types supported by the tool"""
return self.SUPPORTED_FILES
def makefile_setup(self, manifest_project_dict, fileset, filename=None):
def makefile_setup(self, top_manifest, fileset, filename=None):
"""Set the Makefile configuration"""
self.manifest_dict = manifest_project_dict
self.manifest_dict = top_manifest.manifest_dict
self.fileset = fileset
if filename:
self._filename = filename
......
hdlmake/tools/makefilesim.py
View file @ fad48533
......@@ -10,9 +10,9 @@ from ..util import shell
from ..sourcefiles.srcfile import VerilogFile, VHDLFile, SVFile
def _check_simulation_manifest(manifest_dict):
def _check_simulation_manifest(top_manifest):
"""Check if the simulation keys are provided by the top manifest"""
if manifest_dict.get("sim_top") is None:
if top_manifest.manifest_dict.get("sim_top") is None:
raise Exception("sim_top variable must be set in the top manifest.")
......@@ -25,10 +25,10 @@ class MakefileSim(ToolMakefile):
def __init__(self):
super(MakefileSim, self).__init__()
def write_makefile(self, config, fileset, filename=None):
def write_makefile(self, top_manifest, fileset, filename=None):
"""Execute the simulation action"""
_check_simulation_manifest(config)
self.makefile_setup(config, fileset, filename=filename)
_check_simulation_manifest(top_manifest)
self.makefile_setup(top_manifest, fileset, filename=filename)
self.makefile_check_tool('sim_path')
self.makefile_includes()
self._makefile_sim_top()
......
hdlmake/tools/makefilesyn.py
View file @ fad48533
......@@ -10,15 +10,12 @@ from ..util import shell
from ..sourcefiles.srcfile import VerilogFile, SVFile
def _check_synthesis_manifest(manifest_dict):
def _check_synthesis_manifest(top_manifest):
"""Check the manifest contains all the keys for a synthesis project"""
for v in ["syn_device", "syn_grade", "syn_package"]:
if v not in manifest_dict:
for v in ["syn_top", "syn_device", "syn_grade", "syn_package"]:
if v not in top_manifest.manifest_dict:
raise Exception(
"'{}' variable must be set in the top manifest.".format(v))
if not manifest_dict["syn_top"]:
logging.error(
"syn_top variable must be set in the top manifest.")
class MakefileSyn(ToolMakefile):
......@@ -29,11 +26,10 @@ class MakefileSyn(ToolMakefile):
super(MakefileSyn, self).__init__()
self._tcl_controls = {}
def write_makefile(self, config, fileset, filename=None):
def write_makefile(self, top_manifest, fileset, filename=None):
"""Generate a Makefile for the specific synthesis tool"""
_check_synthesis_manifest(config)
self.makefile_setup(config, fileset,
filename=filename)
_check_synthesis_manifest(top_manifest)
self.makefile_setup(top_manifest, fileset, filename=filename)
self.makefile_check_tool('syn_path')
self.makefile_includes()
self._makefile_syn_top()
......
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