Add default_nettype to the Verilog preprocessor keywords

f6244ad2 · Javier D. Garcia-Lasheras · 08e18b3b · f6244ad2
Commit f6244ad2 authored Jun 09, 2017 by Javier D. Garcia-Lasheras
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vlog_parser.py hdlmake/vlog_parser.py +1 -0

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--- a/hdlmake/vlog_parser.py
+++ b/hdlmake/vlog_parser.py
@@ -44,6 +44,7 @@ class VerilogPreprocessor(object):

    # Reserved verilog preprocessor keywords. The list is certainly not full
    vpp_keywords = [
+        "default_nettype",
        "define",
        "line",
        "include",