Massive refactoring assisted by autopep8

parent 35cb5526
This diff is collapsed.
......@@ -36,7 +36,9 @@ from hdlmake.env import Env
from hdlmake import new_dep_solver as dep_solver
class Action(list):
"""This is the base class providing the common Action methods"""
def __init__(self, *args):
......@@ -46,7 +48,6 @@ class Action(list):
list.__init__(self, *args)
super(Action, self).__init__(*args)
def new_module(self, parent, url, source, fetchto):
"""Add new module to the pool.
......@@ -73,7 +74,6 @@ class Action(list):
return new_module
def _check_all_fetched_or_quit(self):
"""Check if every module in the pool is fetched"""
if not self.is_everything_fetched():
......@@ -85,7 +85,6 @@ class Action(list):
)
quit()
def _check_manifest_variable_is_set(self, name):
"""Method to check if a specific manifest variable is set"""
if getattr(self.top_module, name) is None:
......@@ -95,7 +94,6 @@ class Action(list):
name, self.__class__.__name__)
sys.exit("\nExiting")
def _check_manifest_variable_value(self, name, value):
"""Method to check if a manifest variable is set to a specific value"""
variable_match = False
......@@ -106,10 +104,9 @@ class Action(list):
if variable_match is False:
logging.error(
"Variable %s must be set in the manifest and equal to '%s'.",
name, value)
name, value)
sys.exit("Exiting")
def build_complete_file_set(self):
"""Build file set with all the files listed in the complete pool"""
logging.debug("Begin build complete file set")
......@@ -120,7 +117,6 @@ class Action(list):
logging.debug("End build complete file set")
return all_manifested_files
def build_file_set(self, top_entity=None):
"""Build file set with only those files required by the top entity"""
logging.debug("Begin build file set for %s", top_entity)
......@@ -134,12 +130,10 @@ class Action(list):
logging.debug("End build file set")
return source_files
def get_top_module(self):
"""Get the Top module from the pool"""
return self.top_module
def get_module_by_path(self, path):
"""Get instance of Module being stored at a given location"""
path = path_mod.rel2abs(path)
......@@ -148,7 +142,6 @@ class Action(list):
return module
return None
def is_everything_fetched(self):
"""Check if every module is already fetched"""
if len([m for m in self if not m.isfetched]) == 0:
......@@ -156,7 +149,6 @@ class Action(list):
else:
return False
def fetch_all(self):
"""Fetch all the modules declared in the design"""
......@@ -188,12 +180,12 @@ class Action(list):
for mod in new_modules:
if not mod.isfetched:
logging.debug("Appended to fetch queue: "
+ str(mod.url))
+ str(mod.url))
self._add(mod)
fetch_queue.append(mod)
else:
logging.debug("NOT appended to fetch queue: "
+ str(mod.url))
+ str(mod.url))
def _add(self, new_module):
"""Add the given new module if this is not already in the pool"""
......@@ -208,7 +200,6 @@ class Action(list):
self.append(new_module)
return True
def __contains(self, module):
"""Check if the pool contains the given module by checking the URL"""
for mod in self:
......@@ -216,7 +207,6 @@ class Action(list):
return True
return False
def _guess_origin(self, path):
"""Guess origin (git, svn, local) of a module at given path"""
cwd = self.top_module.path
......@@ -243,7 +233,6 @@ class Action(list):
finally:
os.chdir(cwd)
def set_environment(self, options):
"""Initialize the module pool environment from the provided options"""
env = Env(options)
......@@ -256,6 +245,3 @@ class Action(list):
def __str__(self):
"""Cast the module list as a list of strings"""
return str([str(m) for m in self])
......@@ -28,7 +28,9 @@ import re
from .action import Action
class ActionCheck(Action):
"""Class providing the method to check general properties"""
def __init__(self, *args):
......@@ -45,6 +47,7 @@ class ActionCheck(Action):
logging.error("This action is not implemented yet!")
quit()
def _compare(local, reference, cond):
"""Function that provides the actual condition line"""
if cond == "==":
......
......@@ -33,7 +33,9 @@ from hdlmake.srcfile import VerilogFile, VHDLFile, NGCFile
from hdlmake.vlog_parser import VerilogPreprocessor
from .action import Action
class ActionCore(Action):
"""Class that contains the methods for core actions"""
def __init__(self, *args):
......@@ -48,12 +50,11 @@ class ActionCore(Action):
os.system(top_module.manifest_dict["fetch_post_cmd"])
logging.info("All modules fetched.")
def clean(self):
"""Delete the local copy of the fetched modules"""
logging.info("Removing fetched modules..")
remove_list = [mod_aux for mod_aux in self if
mod_aux.source in [fetch.GIT, fetch.SVN] and mod_aux.isfetched]
mod_aux.source in [fetch.GIT, fetch.SVN] and mod_aux.isfetched]
remove_list.reverse() # we will remove modules in backward order
if len(remove_list):
for mod_aux in remove_list:
......@@ -64,7 +65,6 @@ class ActionCore(Action):
logging.info("There are no modules to be removed")
logging.info("Modules cleaned.")
def list_files(self):
"""List the files added to the design across the pool hierarchy"""
unfetched_modules = [mod_aux for mod_aux in self
......@@ -75,13 +75,12 @@ class ActionCore(Action):
file_set = self.build_file_set()
file_list = dep_solver.make_dependency_sorted_list(file_set)
files_str = [file_aux.path for file_aux in file_list]
if self.env.options.delimiter == None:
if self.env.options.delimiter is None:
delimiter = "\n"
else:
delimiter = self.env.options.delimiter
print delimiter.join(files_str)
def _print_comment(self, message):
"""Private method that prints a message to stdout if not terse"""
if not self.env.options.terse:
......@@ -96,7 +95,6 @@ class ActionCore(Action):
print "%s\t%s" % (
path_mod.relpath(file_aux.path), "file")
def list_modules(self):
"""List the modules that are contained by the pool"""
......@@ -118,19 +116,18 @@ class ActionCore(Action):
if mod_aux.source in [fetch.SVN, fetch.GIT]:
self._print_comment("# * URL: " + mod_aux.url)
if (mod_aux.source in [fetch.SVN, fetch.GIT, fetch.LOCAL] and
mod_aux.parent):
mod_aux.parent):
self._print_comment("# * The parent for this module is: %s"
% mod_aux.parent.url)
else:
self._print_comment("# * This is the root module")
print "%s\t%s" % (path_mod.relpath(mod_aux.path),
_convert_to_source_name(mod_aux.source))
_convert_to_source_name(mod_aux.source))
if self.env.options.withfiles:
self._print_file_list(mod_aux.files)
self._print_comment("# MODULE END -> %s" % mod_aux.url)
self._print_comment("")
def merge_cores(self):
"""Merge the design into a single VHDL and a single Verilog file"""
self._check_all_fetched_or_quit()
......@@ -147,10 +144,10 @@ class ActionCore(Action):
"-- re-generate the merged version! --\n"
"-----------------------------------------------------------\n"
"\n\n\n\n"
)
)
# Generate a VHDL file containing all the required VHDL files
f_out = open(base+".vhd", "w")
f_out = open(base + ".vhd", "w")
f_out.write(file_header)
for vhdl in flist.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n" % vhdl.rel_path())
......@@ -158,13 +155,13 @@ class ActionCore(Action):
if vhdl.module.revision:
f_out.write("--- Revision: %s\n" % vhdl.module.revision)
f_out.write("--- Last modified: %s\n" %
time.ctime(os.path.getmtime(vhdl.path)))
f_out.write(open(vhdl.rel_path(), "r").read()+"\n\n")
#print("VHDL: %s" % vhdl.rel_path())
time.ctime(os.path.getmtime(vhdl.path)))
f_out.write(open(vhdl.rel_path(), "r").read() + "\n\n")
# print("VHDL: %s" % vhdl.rel_path())
f_out.close()
# Generate a VHDL file containing all the required VHDL files
f_out = open(base+".v", "w")
f_out = open(base + ".v", "w")
f_out.write(file_header)
for vlog in flist.filter(VerilogFile):
f_out.write("\n\n// File: %s\n" % vlog.rel_path())
......@@ -172,7 +169,7 @@ class ActionCore(Action):
if vlog.module.revision:
f_out.write("// Revision: %s\n" % vlog.module.revision)
f_out.write("// Last modified: %s\n" %
time.ctime(os.path.getmtime(vlog.path)))
time.ctime(os.path.getmtime(vlog.path)))
vpp = VerilogPreprocessor()
for include_path in vlog.include_dirs:
vpp.add_path(include_path)
......
......@@ -25,11 +25,13 @@
import os
import string
import platform
from .action import Action
class ActionMakefile(Action):
"""Class that provides the Makefile writing methods and status"""
def __init__(self, filename=None):
......@@ -45,9 +47,6 @@ class ActionMakefile(Action):
if self._file:
self._file.close()
def _print_sim_top(self, top_module):
top_parameter = string.Template("""TOP_MODULE := ${top_module}\n
PWD := $$(shell pwd)""")
......@@ -113,7 +112,6 @@ PWD := $$(shell pwd)""")
" \\\n")
self.write('\n')
def _print_syn_command(self, top_module):
if top_module.manifest_dict["syn_pre_cmd"]:
syn_pre_cmd = top_module.manifest_dict["syn_pre_cmd"]
......@@ -135,7 +133,6 @@ syn_post_cmd:
self.writeln(syn_command.substitute(syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd))
def _print_sim_command(self, top_module):
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
......@@ -157,8 +154,31 @@ sim_post_cmd:
self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd))
def _print_clean(self, clean_targets):
"""Print the Makefile clean target"""
if platform.system() == 'Windows':
del_command = "rm -rf"
else:
del_command = "rm -rf"
self.writeln("#target for cleaning intermediate files")
self.writeln("clean:")
tmp = "\t\t" + del_command + \
" $(LIBS) " + ' '.join(clean_targets["clean"])
self.writeln(tmp)
self.writeln()
self.writeln("#target for cleaning final files")
self.writeln("mrproper: clean")
tmp = "\t\t" + del_command + \
" " + ' '.join(clean_targets["mrproper"])
self.writeln(tmp)
self.writeln()
def _print_sim_phony(self, top_module):
self.writeln(".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
"""Print simulation PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
def initialize(self):
......@@ -192,4 +212,3 @@ sim_post_cmd:
self.write("\n")
else:
self.write(text + "\n")
......@@ -30,8 +30,11 @@ import logging
from .action import Action
class QsysHwTclUpdate(Action):
"""Class providing methods to update a set of Altera Qsys HW TCL files"""
def __init__(self, *args):
super(QsysHwTclUpdate, self).__init__(*args)
......@@ -52,7 +55,8 @@ class QsysHwTclUpdate(Action):
file_tcl[-1] += " TOP_LEVEL_FILE"
file_tcl.append("\n")
hw_tcl_filename = self.get_top_module().manifest_dict["hw_tcl_filename"]
hw_tcl_filename = self.get_top_module().manifest_dict[
"hw_tcl_filename"]
infile = open(hw_tcl_filename, "r")
inserted = True
......
......@@ -27,7 +27,7 @@ import logging
import sys
from hdlmake.dep_file import DepFile
#import hdlmake.new_dep_solver as dep_solver
# import hdlmake.new_dep_solver as dep_solver
from hdlmake.tools import (
ToolIVerilog, ToolISim, ToolModelsim,
......@@ -36,7 +36,8 @@ from hdlmake.tools import (
class ActionSimulation(
ToolIVerilog, ToolISim, ToolModelsim,
ToolActiveHDL, ToolRiviera, ToolGHDL):
ToolActiveHDL, ToolRiviera, ToolGHDL):
"""This class contains the simulation specific methods"""
def __init__(self, *args):
......@@ -51,7 +52,6 @@ class ActionSimulation(
logging.error("sim_tool variable must be set in the top manifest.")
sys.exit("Exiting")
def simulation_makefile(self):
"""Execute the simulation action"""
self._check_all_fetched_or_quit()
......@@ -83,10 +83,9 @@ class ActionSimulation(
self.env.check_tool(tool_object)
self.env.check_general()
if self.env[path_key] is None and self.env.options.force is not True:
logging.error("Can't generate a " + name + " makefile. " +
bin_name + " not found.")
bin_name + " not found.")
sys.exit("Exiting")
logging.info("Generating " + name + " makefile for simulation.")
......@@ -95,15 +94,15 @@ class ActionSimulation(
fset = self.build_file_set(top_module.manifest_dict["sim_top"])
dep_files = fset.filter(DepFile)
#dep_solver.solve(dep_files)
# dep_solver.solve(dep_files)
#tool_object.generate_simulation_makefile(dep_files, top_module)
# tool_object.generate_simulation_makefile(dep_files, top_module)
tool_object._print_sim_top(top_module)
tool_object._print_sim_options(top_module)
tool_object._print_sim_local(top_module)
tool_object._print_sim_sources(dep_files)
tool_object._print_sim_compilation(dep_files, top_module)
tool_object._print_sim_command(top_module)
tool_object._print_clean(top_module)
tool_object._print_clean(tool_object.CLEAN_TARGETS)
tool_object._print_sim_phony(top_module)
......@@ -34,9 +34,11 @@ from hdlmake.tools import (
ToolISE, ToolPlanAhead, ToolVivado,
ToolQuartus, ToolDiamond, ToolLibero)
class ActionSynthesis(
ToolISE, ToolPlanAhead, ToolVivado,
ToolQuartus, ToolDiamond, ToolLibero):
ToolQuartus, ToolDiamond, ToolLibero):
"""Class providing the public synthesis methods for the user"""
def __init__(self, *args):
......@@ -61,7 +63,6 @@ class ActionSynthesis(
logging.error("Synthesis tool not recognized: %s", tool_name)
return tool_object
def _check_synthesis_makefile(self):
"""Check the manifest contains all the keys for a synthesis makefile"""
# NOTE: top_module is not used in synthesis!!
......@@ -72,7 +73,6 @@ class ActionSynthesis(
logging.error("syn_tool variable must be set in the top manifest.")
sys.exit("Exiting")
def synthesis_makefile(self):
"""Generate a synthesis Makefile for the selected tool"""
self._check_all_fetched_or_quit()
......@@ -98,7 +98,6 @@ class ActionSynthesis(
tool_path=tool_path)
logging.info("Synthesis makefile generated.")
def _write_project_vhd(self, tool, version):
"""Create a VHDL file containing a SDB compatible design description"""
from string import Template
......@@ -161,16 +160,15 @@ end sdb_meta_pkg;""")
syn_module_name=self.top_module.manifest_dict["syn_top"],
syn_commit_id=self.top_module.revision,
syn_tool_name=tool.upper(),
syn_tool_version="0000"*(8-len(syn_tool_std_logic_vector)) +
syn_tool_version="0000" * (8 - len(syn_tool_std_logic_vector)) +
''.join(syn_tool_std_logic_vector),
syn_tool_version_str=syn_tool_version,
syn_tool_version_str=syn_tool_version,
syn_date=''.join(date_std_logic_vector),
syn_date_str=date_string,
syn_date_str=date_string,
syn_username=getpass.getuser())
project_vhd.write(template)
project_vhd.close()
def _check_synthesis_project(self):
"""Check the manifest contains all the keys for a synthesis project"""
manifest = self.get_top_module().manifest_dict
......@@ -195,7 +193,6 @@ end sdb_meta_pkg;""")
"syn_top variable must be set in the top manifest.")
sys.exit("Exiting")
def synthesis_project(self):
"""Generate a project for the specific synthesis tool"""
self._check_all_fetched_or_quit()
......@@ -238,7 +235,6 @@ end sdb_meta_pkg;""")
top_mod = self.get_top_module()
fileset = self.build_file_set(top_mod.manifest_dict["syn_top"])
sup_files = self.build_complete_file_set()
privative_files = []
for file_aux in sup_files:
......@@ -246,10 +242,9 @@ end sdb_meta_pkg;""")
for file_type in tool_object.SUPPORTED_FILES):
privative_files.append(file_aux)
if len(privative_files) > 0:
logging.info("Detected %d supported files that are not parseable",
len(privative_files))
fileset.add(privative_files)
logging.info("Detected %d supported files that are not parseable",
len(privative_files))
fileset.add(privative_files)
sff = SourceFileFactory()
if self.env.options.generate_project_vhd:
......@@ -258,9 +253,9 @@ end sdb_meta_pkg;""")
module=self.get_module_by_path("."))])
tool_object.generate_synthesis_project(update=update,
tool_version=self.env[version_key],
top_mod=self.get_top_module(),
fileset=fileset)
tool_version=self.env[
version_key],
top_mod=self.get_top_module(),
fileset=fileset)
logging.info(name + " project file generated.")
......@@ -27,7 +27,9 @@ import logging
from .action import Action
class ActionTree(Action):
"""Class providing methods to create a graph from pool and to analyze it"""
def __init__(self, *args):
......@@ -48,7 +50,6 @@ class ActionTree(Action):
json_file.write(json_string)
json_file.close()
def _generate_tree_graphviz(self, hierarchy, top_id):
"""Define the program used to write the graphviz:
Program should be one of:
......@@ -66,13 +67,12 @@ class ActionTree(Action):
prog=self.env.options.graphviz,
root=top_id)
nx.draw(hierarchy, pos,
with_labels=True,
alpha=0.5,
node_size=100)
with_labels=True,
alpha=0.5,
node_size=100)
plt.savefig("hierarchy.png")
plt.show()
def generate_tree(self):
"""Generate the graph from pool and create the requested outcomes"""
try:
......@@ -108,5 +108,3 @@ class ActionTree(Action):
self._generate_tree_web(hierarchy, top_id)
self._generate_tree_graphviz(hierarchy, top_id)
......@@ -39,7 +39,12 @@ class DepRelation(object):
def __init__(self, obj_name, direction, rel_type):
assert direction in [DepRelation.PROVIDE, DepRelation.USE]
assert rel_type in [DepRelation.ENTITY, DepRelation.PACKAGE, DepRelation.INCLUDE, DepRelation.ARCHITECTURE, DepRelation.MODULE]
assert rel_type in [
DepRelation.ENTITY,
DepRelation.PACKAGE,
DepRelation.INCLUDE,
DepRelation.ARCHITECTURE,
DepRelation.MODULE]
self.direction = direction
self.rel_type = rel_type
self.obj_name = obj_name.lower()
......@@ -64,7 +69,12 @@ class DepRelation(object):
def __repr__(self):
dstr = {self.USE: "Use", self.PROVIDE: "Provide"}
ostr = {self.ENTITY: "entity", self.PACKAGE: "package", self.INCLUDE: "include/header", self.ARCHITECTURE: "architecture", self.MODULE: "module"}
ostr = {
self.ENTITY: "entity",
self.PACKAGE: "package",
self.INCLUDE: "include/header",
self.ARCHITECTURE: "architecture",
self.MODULE: "module"}
return "%s %s '%s'" % (dstr[self.direction], ostr[self.rel_type], self.obj_name)
def __hash__(self):
......@@ -79,6 +89,7 @@ class DepRelation(object):
class File(object):
def __init__(self, path, module=None):
self.path = path
assert not isinstance(module, basestring)
......@@ -135,11 +146,12 @@ class File(object):
def extension(self):
tmp = self.path.rsplit('.')
ext = tmp[len(tmp)-1]
ext = tmp[len(tmp) - 1]
return ext
class DepFile(File):
def __init__(self, file_path, module):
from hdlmake.module import Module
assert isinstance(file_path, basestring)
......@@ -150,7 +162,9 @@ class DepFile(File):
self._rels = set()
self._inputs = set()
self._outputs = set()
self.depends_on = set() # set of files that the file depends on, items of type DepFile
self.depends_on = set()
# set of files that the file depends on, items of
# type DepFile
self.dep_level = None
self.is_parsed = False
self.file_path = file_path
......@@ -164,9 +178,9 @@ class DepFile(File):
parser = ParserFactory().create(self)
parser.parse(self)
#use proxy template here
# use proxy template here
def __get_rels(self):
#self._parse_if_needed()
# self._parse_if_needed()
return self._rels
def __set_rels(self, what):
......@@ -179,11 +193,11 @@ class DepFile(File):
def satisfies(self, rel_b):
assert isinstance(rel_b, DepRelation)
#self._parse_if_needed()
# self._parse_if_needed()
return any(map(lambda x: x.satisfies(rel_b), self.rels))
def show_relations(self):
#self._parse_if_needed()
# self._parse_if_needed()
for r in self.rels:
print(str(r))
......@@ -192,15 +206,19 @@ class DepFile(File):
return os.path.basename(self.file_path)
def get_dep_level(self):
if self.dep_level == None:
if self.dep_level is None:
if len(self.depends_on) == 0:
self.dep_level = 0
else:
# set dep_level to a negative value so we can detect if the recusion below brings us back to
# this file in a circular reference, that would otherwise result in an infinite loop.
# this file in a circular reference, that would otherwise
# result in an infinite loop.
self.dep_level = -1
# recurse, to find the largest number of levels below.
self.dep_level = 1 + max([dep.get_dep_level() for dep in self.depends_on]);
self.dep_level = 1 + \
max([dep.get_dep_level() for dep in self.depends_on])
elif self.dep_level < 0:
logging.warning("Probably run into a circular reference of file dependencies. It appears %s depends on itself, indirectly via atleast one other file." % self.file_path)
logging.warning(
"Probably run into a circular reference of file dependencies. It appears %s depends on itself, indirectly via atleast one other file." %
self.file_path)
return self.dep_level
......@@ -37,6 +37,7 @@ _plain_print = print
class _PrintClass(object):
def __init__(self):
self.verbose = None
......@@ -48,7 +49,7 @@ class _PrintClass(object):
_plain_print(*args, **kwargs)
print = _PrintClass()
_64bit_architecture = sys.maxsize > 2**32
_64bit_architecture = sys.maxsize > 2 ** 32
def _green(text):
......@@ -61,34 +62,34 @@ def _red(text):
class Env(dict):
#def __init__(self, options, top_module=None):
# def __init__(self, options, top_module=None):
def __init__(self, options):
dict.__init__(self)
self.options = options
#self.top_module = top_module
# self.top_module = top_module
def check_env(self, verbose=True):
print.set_verbose(verbose)
# Check and determine general environment
self.check_general()
def _get(self, name):
assert not name.startswith("HDLMAKE_")
assert isinstance(name, basestring)
name = name.upper()
return os.environ.get("HDLMAKE_%s" % name)
def _get_path(self, name):
if platform.system() == 'Windows': which_cmd = "where"
else: which_cmd = "which"
location = os.popen(which_cmd + " %s" % name).read().split('\n', 1)[0].strip()
if platform.system() == 'Windows':
which_cmd = "where"
else:
which_cmd = "which"
location = os.popen(
which_cmd + " %s" %
name).read().split('\n', 1)[0].strip()
logging.debug("location for %s: %s" % (name, location))
return os.path.dirname(location)
def _is_in_path(self, name, path=None):
if path is not None:
return os.path.exists(os.path.join(path, name))
......@@ -97,7 +98,6 @@ class Env(dict):
path = self._get_path(name)
return len(path) > 0
def _check_in_system_path(self, name):
path = self._get_path(name)
if path:
......@@ -105,7 +105,6 @@ class Env(dict):
else:
return False
def check_general(self):
self["architecture"] = 64 if _64bit_architecture else 32
self["platform"] = sys.platform
......@@ -116,13 +115,15 @@ class Env(dict):
print("### General variabless ###")
self._report_and_set_hdlmake_var("coredir")
if self["coredir"] is not None:
print("All modules will be fetched to %s" % path.rel2abs(self["coredir"]))
print(
"All modules will be fetched to %s" %
path.rel2abs(self["coredir"]))
else:
print("'fetchto' variables in the manifests will be respected when fetching.")
print(
"'fetchto' variables in the manifests will be respected when fetching.")
def check_tool(self, info_class):
tool_info = info_class.TOOL_INFO
if sys.platform == 'cygwin':
bin_name = tool_info['windows_bin']
......@@ -137,36 +138,45 @@ class Env(dict):
self._report_and_set_hdlmake_var(path_key)
if self[path_key] is not None:
if self._is_in_path(bin_name, self[path_key]):
print(name + " " + _green("found") + " under HDLMAKE_" + path_key.upper() + ": %s" % self[path_key])
print(
name + " " + _green("found") + " under HDLMAKE_" + path_key.upper() + ": %s" %
self[path_key])
else:
print(name + " " + _red("NOT found") + " under HDLMAKE_" + path_key.upper() + ": %s" % self[path_key])
print(
name + " " + _red("NOT found") + " under HDLMAKE_" + path_key.upper() + ": %s" %
self[path_key])
else:
if self._check_in_system_path(bin_name):
self[path_key] = self._get_path(bin_name)
print(name + " " + _green("found") + " in system path: %s" % self[path_key])
print(
name + " " + _green("found") + " in system path: %s" %
self[path_key])
else:
print(name + " " + _red("cannnot") + " be found.")
if self[path_key] is not None:
self[version_key] = info_class.detect_version(self[path_key])
print("Detected " + name +" version %s" % self[version_key])
print("Detected " + name + " version %s" % self[version_key])
def _report_and_set_hdlmake_var(self, name):
name = name.upper()
val = self._get(name)
if val:
print(("Environmental variable HDLMAKE_%s " + _green("is set:") + ' "%s".') % (name, val))
print(
("Environmental variable HDLMAKE_%s " + _green("is set:") + ' "%s".') %
(name, val))
self[name.lower()] = val
return True
else:
print(("Environmental variable HDLMAKE_%s " + _red("is not set.")) % name)
print(
("Environmental variable HDLMAKE_%s " + _red("is not set.")) %
name)
self[name.lower()] = None
return False
## TODO: TRANSFORM THIS INTO A GENERAL VERSION FORCE/CHECK MECHANISM OR SUPRESS???
#def check_env_wrt_manifest(self, verbose=False):
# # determine ISE version
# TODO: TRANSFORM THIS INTO A GENERAL VERSION FORCE/CHECK MECHANISM OR SUPRESS???
# def check_env_wrt_manifest(self, verbose=False):
# determine ISE version
# if self.top_module:
# if self.top_module.syn_ise_version is not None:
# ise_version = self.top_module.syn_ise_version
......@@ -178,7 +188,6 @@ class Env(dict):
# " guessed ISE version: %s.%s." % (iv[0], iv[1]))
if __name__ == "__main__":
ec = Env({}, {})
ec.check()
......@@ -23,4 +23,3 @@ from .constants import (GIT, SVN, LOCAL, fetch_type_lookup)
from .git import Git
from .svn import Svn
from .backend_factory import BackendFactory
......@@ -22,14 +22,16 @@
import logging
from .constants import (LOCAL)
class BackendFactory(object):
def __init__(self):
self.backend_table = {}
def register_backend(self, backend_id, backend):
"""Add a mapping: backend_id -> backend"""
self.backend_table[backend_id] = backend
def get_backend(self, module):
try:
if module.source != LOCAL:
......@@ -38,8 +40,8 @@ class BackendFactory(object):
backend = self.backend_table[module.source]
except KeyError:
error_string = "No registered backend found for module: " +\
str(module) + "\n" +\
"Registered backends are:\n"
str(module) + "\n" +\
"Registered backends are:\n"
for backend_id in self.backend_table.iterkeys():
error_string += "\t%d" % (backend_id)
logging.error(error_string)
......
......@@ -33,7 +33,8 @@ from .local import Local
from .backend_factory import BackendFactory
# Initialize an instance of BackendFactory which will be made publicly available
# Initialize an instance of BackendFactory which will be made publicly
# available
fetch_type_lookup = BackendFactory()
fetch_type_lookup.register_backend(GIT, Git)
fetch_type_lookup.register_backend(SVN, Svn)
......
......@@ -21,5 +21,6 @@
class Fetcher(object):
def fetch(self, module):
pass
\ No newline at end of file
pass
......@@ -30,6 +30,7 @@ from .fetcher import Fetcher
class Git(Fetcher):
def __init__(self):
pass
......@@ -41,15 +42,14 @@ class Git(Fetcher):
if not os.path.exists(".gitmodules"):
return None
tree_root_cmd = Popen("git rev-parse --show-toplevel",
stdout=PIPE,
stdin=PIPE,
shell=True)
stdout=PIPE,
stdin=PIPE,
shell=True)
tree_root_line = tree_root_cmd.stdout.readlines()[0].strip()
return tree_root_line
finally:
os.chdir(cur_dir)
def fetch(self, module):
fetchto = module.fetchto()
if module.source != GIT:
......@@ -119,7 +119,9 @@ class Git(Fetcher):
close_fds=not is_windows)
errmsg = stderr.readlines()
if errmsg:
logging.debug("git error message (in %s): %s" % (path, '\n'.join(errmsg)))
logging.debug(
"git error message (in %s): %s" %
(path, '\n'.join(errmsg)))
try:
commit = git_out.stdout.readlines()[0].strip()
......
......@@ -21,10 +21,11 @@
from .fetcher import Fetcher
class Local(Fetcher):
def __init__(self):
pass
def fetch(self, module):
pass
\ No newline at end of file
......@@ -29,6 +29,7 @@ from .fetcher import Fetcher
class Svn(Fetcher):
def __init__(self):
pass
......@@ -72,10 +73,18 @@ class Svn(Fetcher):
is_windows = path.check_windows()
os.chdir(path)
svn_cmd = "svn info 2>/dev/null | awk '{if(NR == 5) {print $2}}'"
svn_out = Popen(svn_cmd, shell=True, stdin=PIPE, stdout=PIPE, stderr=stderr, close_fds=not is_windows)
svn_out = Popen(
svn_cmd,
shell=True,
stdin=PIPE,
stdout=PIPE,
stderr=stderr,
close_fds=not is_windows)
errmsg = stderr.readlines()
if errmsg:
logging.debug("svn error message (in %s): %s" % (path, '\n'.join(errmsg)))
logging.debug(
"svn error message (in %s): %s" %
(path, '\n'.join(errmsg)))
try:
revision = svn_out.stdout.readlines()[0].strip()
......
This diff is collapsed.
......@@ -3,4 +3,3 @@
from .core import ModuleCore
from .content import ModuleContent
from .module import Module, ModuleArgs
......@@ -6,8 +6,11 @@ from .core import ModuleCore
from hdlmake import fetch
from hdlmake.util import path as path_mod
class ModuleContent(ModuleCore):
"""Class providing the HDLMake module content"""
def __init__(self):
# Manifest Files Properties
self.files = None
......@@ -33,23 +36,22 @@ class ModuleContent(ModuleCore):
self.files = SourceFileSet()
try:
logging.debug("No files in the manifest at %s",
self.path)
self.path)
except AttributeError:
pass
else:
self.manifest_dict["files"] = path_mod.flatten_list(
self.manifest_dict["files"])
logging.debug("Files in %s: %s",
self.path, str(self.manifest_dict["files"]))
self.path, str(self.manifest_dict["files"]))
paths = self._make_list_of_paths(self.manifest_dict["files"])
self.files = self._create_file_list_from_paths(paths=paths)
def _process_manifest_modules(self):
"""Process the submodules required by the HDLMake module"""
if self.manifest_dict["fetchto"] is not None:
fetchto = path_mod.rel2abs(self.manifest_dict["fetchto"],
self.path)
self.path)
else:
fetchto = self.fetchto()
......@@ -61,7 +63,7 @@ class ModuleContent(ModuleCore):
for path in local_paths:
if path_mod.is_abs_path(path):
logging.error("Found an absolute path (" + path +
") in a manifest(" + self.path + ")")
") in a manifest(" + self.path + ")")
quit()
path = path_mod.rel2abs(path, self.path)
local_mods.append(self.pool.new_module(parent=self,
......@@ -98,7 +100,6 @@ class ModuleContent(ModuleCore):
else:
self.git = []
def _process_manifest_makefiles(self):
"""Get the extra makefiles defined in the HDLMake module"""
# Included Makefiles
......@@ -109,5 +110,3 @@ class ModuleContent(ModuleCore):
included_makefiles_aux = self.manifest_dict["incl_makefiles"][:]
makefiles_paths = self._make_list_of_paths(included_makefiles_aux)
self.incl_makefiles.extend(makefiles_paths)
......@@ -9,8 +9,10 @@ from hdlmake.util import path as path_mod
class ModuleConfig(object):
"""This class containt the base properties and methods that
need to be initialized for a proper behavior"""
def __init__(self):
self.source = None
self.parent = None
......@@ -56,12 +58,12 @@ class ModuleConfig(object):
self.path = path
self.isfetched = True
logging.debug("Module %s (parent: %s) is fetched.",
url, self.parent.path)
url, self.parent.path)
else:
self.path = path
self.isfetched = False
logging.debug("Module %s (parent: %s) is NOT fetched.",
url, self.parent.path)
url, self.parent.path)
else:
self.url, self.branch, self.revision = url, None, None
......@@ -73,7 +75,6 @@ class ModuleConfig(object):
self.path = url
self.isfetched = True
def _check_filepath(self, filepath):
"""Check the provided filepath against several conditions"""
if filepath:
......@@ -96,7 +97,6 @@ class ModuleConfig(object):
self.path, filepath)
return True
def _make_list_of_paths(self, list_of_paths):
"""Get a list with only the valid absolute paths from the provided"""
paths = []
......@@ -106,9 +106,10 @@ class ModuleConfig(object):
return paths
class ModuleCore(ModuleConfig):
"""This is the class providing the module core functionality"""
def __init__(self):
# Universal Manifest Properties
self.library = "work"
......@@ -118,28 +119,24 @@ class ModuleCore(ModuleConfig):
self.manifest_dict = None
super(ModuleCore, self).__init__()
def set_pool(self, pool):
"""Set the associated pool for the module instance"""
self.pool = pool
self.top_module = pool.get_top_module()
def process_manifest(self):
"""Method that process the core manifest section"""
self._process_manifest_universal()
super(ModuleCore, self).process_manifest()
def _process_manifest_universal(self):
"""Method processing the universal manifest directives"""
#if "top_module" in self.manifest_dict:
# if "top_module" in self.manifest_dict:
# self.top_module = self.manifest_dict["top_module"]
# Libraries
self.library = self.manifest_dict["library"]
self.action = self.manifest_dict["action"].lower()
def _create_file_list_from_paths(self, paths):
"""
Build a Source File Set containing the files indicated by the
......@@ -162,4 +159,3 @@ class ModuleCore(ModuleConfig):
module=self,
library=self.library))
return srcs
......@@ -37,7 +37,9 @@ from hdlmake.module import ModuleContent
class ModuleArgs(object):
"""This class is just a container for the main Module args"""
def __init__(self):
self.parent = None
self.url = None
......@@ -57,6 +59,7 @@ class ModuleArgs(object):
class Module(ModuleContent):
"""
This is the class providing the HDLMake module, the basic element
providing the modular behavior allowing for structured designs.
......@@ -72,17 +75,14 @@ class Module(ModuleContent):
self.module_args = ModuleArgs()
self.module_args = module_args
def __str__(self):
return self.url
@property
def is_fetched_to(self):
"""Get the path where the module instance resides"""
return os.path.dirname(self.path)
def submodules(self):
"""Get a list with all the submodules this module instance requires"""
def __nonull(submodule_list):
......@@ -94,7 +94,6 @@ class Module(ModuleContent):
return __nonull(self.local) + __nonull(self.git) \
+ __nonull(self.svn)
def remove_dir_from_disk(self):
"""Delete the module dir if it is already fetched and available"""
if not self.isfetched:
......@@ -119,7 +118,6 @@ class Module(ModuleContent):
super(Module, self).process_manifest()
self._set_simulation_options()
def _set_simulation_options(self):
"""This set the simulation option for all the files in the Module"""
from hdlmake.srcfile import VerilogFile, VHDLFile
......@@ -131,7 +129,6 @@ class Module(ModuleContent):
elif isinstance(file_aux, VHDLFile):
file_aux.vcom_opt = self.manifest_dict["vcom_opt"]
def get_include_dirs_list(self):
"""Private method that processes the included directory list"""
# Include dirs
......@@ -143,7 +140,7 @@ class Module(ModuleContent):
include_dirs.append(dir_list)
else:
dir_list = [path_mod.compose(self.path, x) for
x in self.manifest_dict["include_dirs"]]
x in self.manifest_dict["include_dirs"]]
include_dirs.extend(dir_list)
# Analyze included dirs and report if any issue is found
for dir_ in include_dirs:
......@@ -153,12 +150,9 @@ class Module(ModuleContent):
self.path, dir_)
if not os.path.exists(dir_):
logging.warning(self.path +
" has an unexisting include directory: " + dir_)
" has an unexisting include directory: " + dir_)
return include_dirs
def parse_manifest(self):
"""
Create a dictionary from the module Manifest.py and assign it
......@@ -189,7 +183,7 @@ PARSE START: %s
manifest_parser = ManifestParser()
#manifest_parser.add_arbitrary_code(
# manifest_parser.add_arbitrary_code(
# self.pool.top_module.options.arbitrary_code)
manifest_parser.add_manifest(self.path)
......@@ -224,4 +218,3 @@ PARSE END: %s
***********************************************************
""", self.path)
......@@ -24,15 +24,16 @@
"""This is the Python module providing the container for the HDL Modules"""
from .action import (ActionCheck, ActionCore,
ActionTree, ActionSimulation,
ActionSynthesis,
QsysHwTclUpdate)
ActionTree, ActionSimulation,
ActionSynthesis,
QsysHwTclUpdate)
class ModulePool(ActionCheck, ActionCore,
ActionTree, ActionSimulation,
ActionSynthesis,
QsysHwTclUpdate):
"""
The ModulePool class acts as the container for the HDLMake modules that
are progressively being added to the design hierarchy.
......@@ -45,5 +46,3 @@ class ModulePool(ActionCheck, ActionCore,
ActionSimulation.__init__(self, *args)
ActionSynthesis.__init__(self, *args)
QsysHwTclUpdate.__init__(self, *args)
......@@ -27,7 +27,9 @@ import logging
from .dep_file import DepFile
from .srcfile import VHDLFile, VerilogFile, SVFile
class DepParser(object):
def __init__(self, dep_file):
self.dep_file = dep_file
......@@ -36,20 +38,23 @@ class DepParser(object):
class ParserFactory(object):
def create(self, dep_file):
import re
from .vlog_parser import VerilogParser
from .vhdl_parser import VHDLParser
if isinstance(dep_file, VHDLFile) :
if isinstance(dep_file, VHDLFile):
return VHDLParser(dep_file)
elif isinstance(dep_file, VerilogFile) or isinstance(dep_file, SVFile) :
elif isinstance(dep_file, VerilogFile) or isinstance(dep_file, SVFile):
vp = VerilogParser(dep_file)
for d in dep_file.include_paths:
vp.add_search_path(d)
return vp
else :
raise ValueError("Unrecognized file format : %s" % dep_file.file_path)
else:
raise ValueError(
"Unrecognized file format : %s" %
dep_file.file_path)
def solve(fileset):
......@@ -57,23 +62,23 @@ def solve(fileset):
from .dep_file import DepRelation
assert isinstance(fileset, SourceFileSet)
fset = fileset.filter(DepFile)
#print(fileset)
#print(fset)
# print(fileset)
# print(fset)
not_satisfied = 0
logging.debug("PARSE BEGIN: Here, we will parse all the files in the fileset: no parsing should be done beyond this point")
logging.debug(
"PARSE BEGIN: Here, we will parse all the files in the fileset: no parsing should be done beyond this point")
for investigated_file in fset:
logging.debug("INVESTIGATED FILE: %s" % investigated_file)
investigated_file.parse_if_needed()
logging.debug("PARSE END: now the parsing is done")
logging.debug("SOLVE BEGIN")
for investigated_file in fset:
#logging.info("INVESTIGATED FILE: %s" % investigated_file)
#print(investigated_file.rels)
# logging.info("INVESTIGATED FILE: %s" % investigated_file)
# print(investigated_file.rels)
for rel in investigated_file.rels:
#logging.info("- relation: %s" % rel)
#logging.info("- direction: %s" % rel.direction)
# logging.info("- relation: %s" % rel)
# logging.info("- direction: %s" % rel.direction)
# Only analyze USE relations, we are looking for dependencies
if rel.direction == DepRelation.USE:
satisfied_by = set()
......@@ -83,55 +88,72 @@ def solve(fileset):
investigated_file.depends_on.add(dep_file)
satisfied_by.add(dep_file)
if len(satisfied_by) > 1:
logging.warning("Relation %s satisfied by multpiple (%d) files: %s",
str(rel),
len(satisfied_by),
'\n'.join([file.path for file in list(satisfied_by)]))
logging.warning(
"Relation %s satisfied by multpiple (%d) files: %s",
str(rel),
len(satisfied_by),
'\n'.join([file.path for file in list(satisfied_by)]))
elif len(satisfied_by) == 0:
logging.warning("Relation %s in %s not satisfied by any source file" % (str(rel), investigated_file.name))
logging.warning(
"Relation %s in %s not satisfied by any source file" %
(str(rel), investigated_file.name))
not_satisfied += 1
logging.debug("SOLVE END")
if not_satisfied != 0:
logging.warning("Dependencies solved, but %d relations were not satisfied" % not_satisfied)
logging.warning(
"Dependencies solved, but %d relations were not satisfied" %
not_satisfied)
else:
logging.info("Dependencies solved, all of the relations weres satisfied!")
logging.info(
"Dependencies solved, all of the relations weres satisfied!")
def make_dependency_sorted_list(fileset, purge_unused=True, reverse=False):
"""Sort files in order of dependency.
Files with no dependencies first.
"""Sort files in order of dependency.
Files with no dependencies first.
All files that another depends on will be earlier in the list."""
dependable = [f for f in fileset if isinstance(f, DepFile)]
non_dependable = [f for f in fileset if not isinstance(f, DepFile)]
dependable.sort(key=lambda f: f.file_path.lower()) # Not necessary, but will tend to group files more nicely in the output.
dependable.sort(key=lambda f: f.file_path.lower())
# Not necessary, but will tend to group files more nicely
# in the output.
dependable.sort(key=DepFile.get_dep_level)
sorted_list = non_dependable + dependable
if reverse:
sorted_list = list(reversed(sorted_list))
return sorted_list
def make_dependency_set(fileset, top_level_entity):
logging.info("Create a set of all files required to build the named top_level_entity.")
logging.info(
"Create a set of all files required to build the named top_level_entity.")
from srcfile import SourceFileSet
from dep_file import DepRelation
assert isinstance(fileset, SourceFileSet)
fset = fileset.filter(DepFile)
# Find the file that provides the named top level entity
top_rel_vhdl = DepRelation("%s.%s" % ("work", top_level_entity), DepRelation.PROVIDE, DepRelation.ENTITY)
top_rel_vlog = DepRelation("%s.%s" % ("work", top_level_entity), DepRelation.PROVIDE, DepRelation.MODULE)
top_rel_vhdl = DepRelation(
"%s.%s" %
("work", top_level_entity), DepRelation.PROVIDE, DepRelation.ENTITY)
top_rel_vlog = DepRelation(
"%s.%s" %
("work", top_level_entity), DepRelation.PROVIDE, DepRelation.MODULE)
top_file = None
for chk_file in fset:
for rel in chk_file.rels:
if ((rel == top_rel_vhdl) or (rel == top_rel_vlog)):
top_file = chk_file
break;
break
if top_file:
break
if top_file == None:
logging.critical('Could not find a top level file that provides the top_module="%s". Continuing with the full file set.' % top_level_entity)
if top_file is None:
logging.critical(
'Could not find a top level file that provides the top_module="%s". Continuing with the full file set.' %
top_level_entity)
return fileset
# Collect only the files that the top level entity is dependant on, by walking the dependancy tree.
# Collect only the files that the top level entity is dependant on, by
# walking the dependancy tree.
try:
dep_file_set = set()
file_set = set([top_file])
......@@ -142,7 +164,9 @@ def make_dependency_set(fileset, top_level_entity):
except KeyError:
# no files left
pass
logging.info("Found %d files as dependancies of %s." % (len(dep_file_set), top_level_entity))
#for dep_file in dep_file_set:
logging.info(
"Found %d files as dependancies of %s." %
(len(dep_file_set), top_level_entity))
# for dep_file in dep_file_set:
# logging.info("\t" + str(dep_file))
return dep_file_set
......@@ -48,6 +48,7 @@ class SourceFile(DepFile):
class VHDLFile(SourceFile):
def __init__(self, path, module, library=None, vcom_opt=None):
SourceFile.__init__(self, path=path, module=module, library=library)
if not vcom_opt:
......@@ -66,7 +67,9 @@ class VHDLFile(SourceFile):
class VerilogFile(SourceFile):
def __init__(self, path, module, library=None, vlog_opt=None, include_dirs=None):
def __init__(self, path, module, library=None,
vlog_opt=None, include_dirs=None):
SourceFile.__init__(self, path=path, module=module, library=library)
if not vlog_opt:
self.vlog_opt = ""
......@@ -124,18 +127,22 @@ class XMPFile(File):
# Xilinx Embedded Micro Processor
pass
class PPRFile(File):
# Xilinx PlanAhead Project
pass
class XPRFile(File):
# Xilinx Vivado Project
pass
class BDFile(File):
# Xilinx Block Design
pass
class XCOFile(File):
# Xilinx Core Generator File
pass
......@@ -143,52 +150,64 @@ class XCOFile(File):
# class NGCFile(SourceFile):
# def __init__(self, path, module):
# SourceFile.__init__(self, path=path, module=module)
class NGCFile(File):
# Xilinx Generated Netlist File
pass
class LDFFile(File):
# Lattice Diamond Project File
pass
class LPFFile(File):
# Lattice Preference/Constraint File
pass
class EDFFile(File):
# EDIF Netlist Files
pass
class PDCFile(File):
# Physical Design Constraints
pass
class WBGenFile(File):
pass
class QSFFile(File):
# Quartus Settings File
pass
class BSFFile(File):
# Quartus Block Symbol File
pass
class BDFFile(File):
# Quartus Block Design File
pass
class TDFFile(File):
# Quartus Text Design File
pass
class GDFFile(File):
# Quartus Graphic Design File
pass
class SourceFileSet(set):
def __init__(self):
super(SourceFileSet, self).__init__()
self = []
......@@ -233,15 +252,17 @@ class SourceFileSet(set):
class SourceFileFactory:
def new(self, path, module, library=None, vcom_opt=None, vlog_opt=None, include_dirs=None):
def new(self, path, module, library=None,
vcom_opt=None, vlog_opt=None, include_dirs=None):
if path == "/home/pawel/cern/wr-cores/testbench/top_level/gn4124_bfm.svh":
raise Exception()
if path is None or path == "":
raise RuntimeError("Expected a file path, got: "+str(path))
raise RuntimeError("Expected a file path, got: " + str(path))
if not os.path.isabs(path):
path = os.path.abspath(path)
tmp = path.rsplit('.')
extension = tmp[len(tmp)-1]
extension = tmp[len(tmp) - 1]
logging.debug("add file " + path)
nf = None
......
......@@ -28,6 +28,7 @@ from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile
class ToolActiveHDL(ActionMakefile):
"""Class providing the interface to control an Active-HDL simulation"""
TOOL_INFO = {
......@@ -38,6 +39,10 @@ class ToolActiveHDL(ActionMakefile):
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["run.command", "library.cfg", "work"],
'mrproper': ["*.vcd", "*.asdb"]}
def __init__(self):
super(ToolActiveHDL, self).__init__()
......@@ -47,19 +52,6 @@ class ToolActiveHDL(ActionMakefile):
pass
def _print_clean(self, top_module):
"""Print the Makefile clean target for Aldec Active-HDL simulator"""
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
\t\trm -rf run.command library.cfg work
#target for cleaning final files
mrproper: clean
\t\trm -f *.vcd *.asdb
""")
def _print_sim_compilation(self, fileset, top_module):
"""Print Makefile compilation target for Aldec Active-HDL simulator"""
self.writeln("simulation:")
......@@ -93,4 +85,3 @@ mrproper: clean
"\" >> run.command")
self.writeln()
self.writeln("\t\tvsimsa -do run.command")
......@@ -35,6 +35,7 @@ DIAMOND_STANDARD_LIBS = ['ieee', 'std']
class ToolDiamond(ActionMakefile):
"""Class providing the interface for Lattice Diamond synthesis"""
TOOL_INFO = {
......@@ -120,7 +121,6 @@ mrproper:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def generate_synthesis_project(self, update=False, tool_version='',
top_mod=None, fileset=None):
"""Create project for Lattice Diamond synthesis"""
......@@ -195,7 +195,7 @@ mrproper:
if (isinstance(file_aux, VHDLFile) or
isinstance(file_aux, VerilogFile) or
isinstance(file_aux, SVFile) or
isinstance(file_aux, EDFFile)):
isinstance(file_aux, EDFFile)):
if update:
line = line + '\n' + tmp.format('remove',
file_aux.rel_path())
......@@ -215,4 +215,3 @@ mrproper:
continue
ret.append(line)
return ('\n'.join(ret)) + '\n'
......@@ -29,7 +29,9 @@ from hdlmake.srcfile import VHDLFile
GHDL_STANDARD_LIBS = ['ieee', 'std']
class ToolGHDL(ActionMakefile):
"""Class providing the interface for Lattice Diamond synthesis"""
TOOL_INFO = {
......@@ -40,6 +42,10 @@ class ToolGHDL(ActionMakefile):
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)"],
'mrproper': ["*.vcd"]}
def __init__(self):
super(ToolGHDL, self).__init__()
......@@ -47,7 +53,6 @@ class ToolGHDL(ActionMakefile):
"""Get tool version for GHDL"""
pass
def _print_sim_options(self, top_module):
"""Print the GHDL options to the Makefile"""
if top_module.manifest_dict["ghdl_opt"]:
......@@ -60,19 +65,6 @@ class ToolGHDL(ActionMakefile):
ghdl_opt=ghdl_opt))
def _print_clean(self, top_module):
"""Print the Makefile clean target for GHDL"""
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
\t\trm -rf *.cf *.o $(TOP_MODULE)
#target for cleaning final files
mrproper: clean
\t\trm -r *.vcd
""")
def _print_sim_compilation(self, fileset, top_module):
"""Print the GDHL simulation compilation target"""
self.writeln("simulation:")
......@@ -83,5 +75,3 @@ mrproper: clean
self.writeln("\t\t# Elaborate design")
self.writeln("\t\tghdl -e $(TOP_MODULE)")
self.writeln()
......@@ -58,6 +58,7 @@ ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
class ToolISE(ActionMakefile):
"""Class providing the methods to create and build a Xilinx ISE project"""
TOOL_INFO = {
......@@ -115,7 +116,6 @@ class ToolISE(ActionMakefile):
return None
return ise_version
def generate_synthesis_makefile(self, top_mod, tool_path):
"""Generate a Makefile to handle a synthesis Xilinx ISE project"""
makefile_tmplt = string.Template("""PROJECT := ${project_name}
......@@ -302,9 +302,10 @@ mrproper:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
class StringBuffer(list):
"""Auxiliar class providing a convenient string storage"""
def __init__(self):
self.append("")
self.__blank = re.compile("^[ \t\n]+$")
......@@ -324,7 +325,6 @@ mrproper:
else:
self[len(self) - 1] += what
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
"""Generate a synthesis project for Xilinx ISE"""
......@@ -348,32 +348,27 @@ mrproper:
logging.info("Writing down .xise project file")
self.emit_xml(self.top_mod.manifest_dict["syn_project"])
def add_files(self, files):
"""Add files to the ISE project"""
self.files.extend(files)
def _add_lib(self, lib):
"""Check if a library is in the ISE project before adding it"""
if lib not in self.libs:
self.libs.append(lib)
def add_libs(self, libs):
"""Add a list of libraries to the ISE project"""
for lib_aux in libs:
self._add_lib(lib_aux)
self.libs.remove('work')
def add_property(self, name, value, is_default=False):
"""Add a property to the Xilinx ISE project"""
self.props[name] = ISEProjectProperty(name=name,
value=value,
is_default=is_default)
def add_initial_properties(self):
"""Add initial properties to the Xilinx ISE project"""
self._set_values_from_manifest()
......@@ -383,7 +378,6 @@ mrproper:
self.add_property("Auto Implementation Top", "false")
self.add_property("Create Binary Configuration File", "true")
def _set_values_from_manifest(self):
"""Add the synthesis properties from the Manifest to the project"""
top_module = self.top_mod
......@@ -409,7 +403,6 @@ mrproper:
"Implementation Top Instance Path",
"/" + top_module.manifest_dict["syn_top"])
def _parse_props(self):
"""Parse properties from the existing ISE project"""
properties_temp = self.xml_project.getElementsByTagName("properties")
......@@ -425,7 +418,6 @@ mrproper:
name="properties",
where=self.xml_doc.documentElement)
def _parse_libs(self):
"""Parse libraries from the existing ISE project"""
libraries_temp = self.xml_project.getElementsByTagName("libraries")
......@@ -435,7 +427,6 @@ mrproper:
name="libraries",
where=self.xml_doc.documentElement)
def _load_xml(self, filename):
"""Load Xilinx ISE project as a XML file"""
file_xml = open(filename)
......@@ -462,14 +453,13 @@ mrproper:
self.ise = tuple(
node.getAttribute(
"xil_pn:ise_version").split(
'.'))
'.'))
where.removeChild(node)
except xml.parsers.expat.ExpatError:
pass
file_xml.close()
self._set_values_from_manifest()
def _purge_dom_node(self, name, where):
"""Purge node at the XML file to accomodate a new value"""
try:
......@@ -481,7 +471,6 @@ mrproper:
where.appendChild(new)
return new
def _output_files(self, node):
"""Add the HDL design files to the Xilinx ISE Project"""
for file_aux in self.files:
......@@ -544,7 +533,6 @@ mrproper:
ise_ver_project.setAttribute("xil_pn:schema_version", "2")
node.appendChild(ise_ver_project)
def emit_xml(self, filename=None):
"""Process the required outputs and write an ISE Project"""
if not self.xml_doc:
......@@ -562,7 +550,6 @@ mrproper:
output_file.write('\n'.join(string_buffer))
output_file.close()
def create_empty_project(self):
"""Create an empty XML docmument to accomodate the ISE Project"""
self.xml_doc = XML_IMPL.createDocument(
......@@ -595,6 +582,7 @@ mrproper:
class ISEProjectProperty(object):
"""Class that serves as container for the Xilinx ISE project properties"""
def __init__(self, name, value, is_default=False):
......
......@@ -44,6 +44,7 @@ ISIM_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
class ToolISim(ActionMakefile):
"""Class providing the interface for Xilinx ISim simulator"""
TOOL_INFO = {
......@@ -54,6 +55,12 @@ class ToolISim(ActionMakefile):
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["./xilinxsim.ini $(LIBS)", "fuse.xmsgs",
"fuse.log", "fuseRelaunch.cmd", "isim",
"isim.log", "isim.wdb", "isim_proj",
"isim_proj.*"],
'mrproper': ["*.vcd"]}
def __init__(self):
super(ToolISim, self).__init__()
......@@ -73,7 +80,6 @@ class ToolISim(ActionMakefile):
return None
return isim_version
def _print_sim_top(self, top_module):
"""Print the top section of the Makefile for Xilinx ISim"""
self.writeln("""## variables #############################
......@@ -82,30 +88,18 @@ TOP_MODULE := """ + top_module.manifest_dict["sim_top"] + """
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) +
"""
"""
""")
def _print_sim_options(self, top_module):
"""Print the Xilinx ISim simulation options in the Makefile"""
self.writeln("""VHPCOMP_FLAGS := -intstyle default \
-incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
self.__get_rid_of_isim_incdirs(
top_module.manifest_dict["vlog_opt"]) + """
""")
def _print_clean(self, top_module):
"""Print the Makefile clean target for Xilinx ISim simulator"""
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
\t\trm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \
isim.wdb isim_proj isim_proj.*
#target for cleaning final files
mrproper: clean
self.__get_rid_of_isim_incdirs(
top_module.manifest_dict["vlog_opt"]) + """
""")
......@@ -245,7 +239,6 @@ fuse:
self.write('\n')
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@\n")
def __get_rid_of_isim_incdirs(self, vlog_opt):
"""Clean the vlog options from include dirs"""
if not vlog_opt:
......@@ -263,7 +256,6 @@ fuse:
skip = True
return ' '.join(ret)
def __get_xilinxsim_ini_dir(self, env):
"""Get Xilinx ISim ini simulation file"""
if env["isim_path"]:
......@@ -286,4 +278,3 @@ fuse:
os_prefix + arch_sufix))
# Ensure the path is absolute and normalized
return os.path.abspath(xilinx_ini_path)
......@@ -39,6 +39,7 @@ IVERILOG_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
class ToolIVerilog(ActionMakefile):
"""Class providing the interface for Icarus Verilog simulator"""
TOOL_INFO = {
......@@ -49,9 +50,14 @@ class ToolIVerilog(ActionMakefile):
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["run.command", "ivl_vhdl_work"],
'mrproper': ["*.vcd", "*.vvp"]}
def __init__(self):
super(ToolIVerilog, self).__init__()
def detect_version(self, path):
"""Get version from Icarus Verilog program"""
is_windows = path_mod.check_windows()
......@@ -63,6 +69,7 @@ class ToolIVerilog(ActionMakefile):
version = iverilog.stdout.readlines()[0].strip()
return version
def _print_sim_compilation(self, fileset, top_module):
"""Generate compile simulation Makefile target for IVerilog"""
......@@ -81,7 +88,11 @@ class ToolIVerilog(ActionMakefile):
self.writeln("\t\techo \"" + vhdl.rel_path() + "\" >> run.command")
for svlog in fileset.filter(SVFile):
self.writeln("\t\techo \"" + svlog.rel_path() + "\" >> run.command")
self.writeln(
"\t\techo \"" +
svlog.rel_path(
) +
"\" >> run.command")
self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command")
......@@ -97,16 +108,3 @@ class ToolIVerilog(ActionMakefile):
self.writeln(iverilog_string.substitute(
iverilog_opt=iverilog_opt))
def _print_clean(self, top_module):
"""Print the Makefile clean target for Icarus Verilog"""
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
\t\trm -rf run.command ivl_vhdl_work
#target for cleaning final files
mrproper: clean
\t\trm -f *.vcd *.vvp
""")
......@@ -36,6 +36,7 @@ LIBERO_STANDARD_LIBS = ['ieee', 'std']
class ToolLibero(ActionMakefile):
"""Class providing the interface for Microsemi Libero IDE synthesis"""
TOOL_INFO = {
......@@ -121,7 +122,6 @@ mrproper:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
"""Create a Microsemi Libero IDE synthesis project"""
......@@ -196,7 +196,7 @@ mrproper:
# First stage: linking files
for file_aux in self.files:
if (isinstance(file_aux, VHDLFile) or
isinstance(file_aux, VerilogFile)):
isinstance(file_aux, VerilogFile)):
line = link_string.format('-hdl_source', file_aux.rel_path())
elif isinstance(file_aux, SDCFile):
line = link_string.format('-sdc', file_aux.rel_path())
......@@ -230,4 +230,3 @@ mrproper:
line = 'set_root -module {' + self.syn_top + '::work}'
ret.append(line)
return ('\n'.join(ret)) + '\n'
......@@ -33,16 +33,18 @@ MODELSIM_STANDARD_LIBS = ['ieee', 'std', 'altera_mf']
class ToolModelsim(VsimMakefileWriter):
"""Class providing the interface for Mentor Modelsim simulator"""
TOOL_INFO = {
'name': 'Modelsim',
'id': 'modelsim',
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
TOOL_INFO = {'name': 'Modelsim',
'id': 'modelsim',
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["./modelsim.ini", "transcript"],
'mrproper': ["*.vcd", "*.wlf"]}
def __init__(self):
super(ToolModelsim, self).__init__()
......@@ -52,14 +54,11 @@ class ToolModelsim(VsimMakefileWriter):
self.copy_rules["modelsim.ini"] = os.path.join(
"$(MODELSIM_INI_PATH)", "modelsim.ini")
self.additional_deps.append("modelsim.ini")
self.additional_clean.extend(
["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
def detect_version(self, path):
"""Get version from the Mentor Modelsim program"""
pass
def _print_sim_options(self, top_module):
"""Print the Modelsim options to the Makefile"""
if top_module.pool.env["modelsim_path"]:
......@@ -71,4 +70,3 @@ class ToolModelsim(VsimMakefileWriter):
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
super(ToolModelsim, self)._print_sim_options(top_module)
......@@ -38,8 +38,8 @@ PLANAHEAD_STANDARD_LIBS = ['ieee', 'std']
class ToolPlanAhead(ActionMakefile):
"""Class providing the interface for Xilinx PlanAhead synthesis"""
"""Class providing the interface for Xilinx PlanAhead synthesis"""
TOOL_INFO = {
'name': 'PlanAhead',
......@@ -129,7 +129,6 @@ mrproper:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
"""Create a Xilinx PlanAhead project"""
......@@ -248,7 +247,7 @@ mrproper:
isinstance(file_aux, UCFFile) or
isinstance(file_aux, NGCFile) or
isinstance(file_aux, XMPFile) or
isinstance(file_aux, XCOFile)):
isinstance(file_aux, XCOFile)):
line = tmp.format(file_aux.rel_path())
else:
continue
......@@ -257,6 +256,7 @@ mrproper:
class _PlanAheadProjectProperty(object):
"""Class that serves as a convenient storage for PlanAhead properties"""
def __init__(self, name=None, value=None, objects=None):
......
......@@ -39,6 +39,7 @@ QUARTUS_STANDARD_LIBS = ['altera', 'altera_mf', 'lpm', 'ieee', 'std']
class ToolQuartus(ActionMakefile):
"""Class providing the interface for Altera Quartus synthesis"""
TOOL_INFO = {
......@@ -134,7 +135,6 @@ mrproper:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def _set_tcl_files(self, mod):
"""Method that checks if the TCL files declared by the module
manifest dictionary exists and if so create them and
......@@ -250,7 +250,6 @@ mrproper:
ret.append(line)
return ('\n'.join(ret)) + '\n'
def add_property(self, val):
"""Add Altera Quartus property to the set of already existing ones"""
# don't save files (they are unneeded)
......@@ -357,19 +356,20 @@ mrproper:
q_prop = _QuartusProjectProperty
self.add_property(
q_prop(q_prop.SET_GLOBAL_ASSIGNMENT,
name_type='FAMILY',
name='"' + syn_family + '"'))
name_type='FAMILY',
name='"' + syn_family + '"'))
self.add_property(
q_prop(q_prop.SET_GLOBAL_ASSIGNMENT,
name_type='DEVICE',
name=devstring))
name_type='DEVICE',
name=devstring))
self.add_property(
q_prop(q_prop.SET_GLOBAL_ASSIGNMENT,
name_type='TOP_LEVEL_ENTITY',
name=syn_top))
name_type='TOP_LEVEL_ENTITY',
name=syn_top))
class _QuartusProjectProperty(object):
"""Class that serves as a container for Altera Quartus properties"""
SET_GLOBAL_INSTANCE = 0
......@@ -413,4 +413,3 @@ class _QuartusProjectProperty(object):
words.append("-section_id")
words.append(self.section_id)
return ' '.join(words)
......@@ -63,6 +63,7 @@ RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolRiviera(VsimMakefileWriter):
"""Class providing the interface for Aldec Riviera-PRO simulator"""
TOOL_INFO = {
......@@ -73,12 +74,14 @@ class ToolRiviera(VsimMakefileWriter):
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["*.asdb"],
'mrproper': ["*.vcd"]}
def __init__(self):
super(ToolRiviera, self).__init__()
self.vcom_flags.append("-2008")
self.additional_clean.extend(["*.asdb", "*.vcd", ])
def detect_version(self, path):
"""Get version from Aldec Riviera-PRO binary program"""
pass
......@@ -55,15 +55,11 @@ class VsimMakefileWriter(ActionMakefile):
# Additional sim dependencies (e.g. modelsim.ini)
self.additional_deps = []
# Additional things removed during a clean e.g. simulator temp files
self.additional_clean = []
# These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path
self.copy_rules = {}
super(VsimMakefileWriter, self).__init__()
def _print_sim_options(self, top_module):
"""Print the vsim options to the Makefile"""
self.vlog_flags.append(
......@@ -82,18 +78,6 @@ class VsimMakefileWriter(ActionMakefile):
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
def _print_clean(self, top_module):
"""Print the Makefile clean target"""
if platform.system() == 'Windows':
del_command = "rm -rf"
else:
del_command = "rm -rf"
self.writeln("clean:")
tmp = "\t\t" + del_command + \
" $(LIBS) " + ' '.join(self.additional_clean)
self.writeln(tmp)
self.writeln("#target for cleaning final files")
self.writeln("mrproper: clean")
def _print_sim_compilation(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
......@@ -141,14 +125,14 @@ class VsimMakefileWriter(ActionMakefile):
self.write(lib + slash_char + "." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command,
lib, "&&", "touch", lib + slash_char + "." + lib, ")"]))
lib, "&&", "touch", lib + slash_char + "." + lib, ")"]))
self.write(' '.join(["||", del_command, lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
for vlog in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vlog.library, vlog.purename,
".%s_%s" % (vlog.purename, vlog.extension())), vlog.rel_path()))
".%s_%s" % (vlog.purename, vlog.extension())), vlog.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile
in vlog.depends_on if dfile is not vlog]:
......@@ -156,7 +140,7 @@ class VsimMakefileWriter(ActionMakefile):
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library,
name, ".%s_%s" % (name, extension)))
name, ".%s_%s" % (name, extension)))
else: # the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
......@@ -172,7 +156,7 @@ class VsimMakefileWriter(ActionMakefile):
# self.writeln(vlog.vlog_opt+" $<")
compile_template = string.Template("\t\tvlog -work ${library}"
" $$(VLOG_FLAGS) ${sv_option} $${INCLUDE_DIRS} $$<")
" $$(VLOG_FLAGS) ${sv_option} $${INCLUDE_DIRS} $$<")
compile_line = compile_template.substitute(
library=vlog.library, sv_option="-sv"
if isinstance(vlog, SVFile) else "")
......@@ -187,7 +171,7 @@ class VsimMakefileWriter(ActionMakefile):
purename = vhdl.purename
# each .dat depends on corresponding .vhd file
self.write("%s: %s" % (os.path.join(lib, purename, "." +
purename + "_" + vhdl.extension()), vhdl.rel_path()))
purename + "_" + vhdl.extension()), vhdl.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in vhdl.depends_on
if dfile is not vhdl]:
......@@ -226,4 +210,3 @@ class VsimMakefileWriter(ActionMakefile):
if not vlog_aux.startswith("+incdir+"):
ret.append(vlog_aux)
return ' '.join(ret)
......@@ -38,6 +38,7 @@ VIVADO_STANDARD_LIBS = ['ieee', 'std']
class ToolVivado(ActionMakefile):
"""Class providing the interface for Xilinx Vivado synthesis"""
TOOL_INFO = {
......@@ -245,7 +246,7 @@ mrproper:
isinstance(file_aux, NGCFile) or
isinstance(file_aux, XMPFile) or
isinstance(file_aux, XCOFile) or
isinstance(file_aux, BDFile)):
isinstance(file_aux, BDFile)):
line = tmp.format(file_aux.rel_path())
elif isinstance(file_aux, TCLFile):
line = tcl.format(file_aux.rel_path())
......@@ -256,6 +257,7 @@ mrproper:
class _VivadoProjectProperty(object):
"""Class providing an storage for Xilinx Vivado properties"""
def __init__(self, name=None, value=None, objects=None):
......@@ -268,4 +270,3 @@ class _VivadoProjectProperty(object):
tmp = "set_property {0} {1} [{2}]"
line = tmp.format(self.name, self.value, self.objects)
return line
......@@ -37,6 +37,7 @@ def stdoutIO(stdout=None):
class ConfigParser(object):
"""Class for parsing python configuration files
Case1: Normal usage
......@@ -133,6 +134,7 @@ class ConfigParser(object):
"""
class Option:
def __init__(self, name, **others):
self.name = name
self.keys = []
......@@ -187,7 +189,12 @@ class ConfigParser(object):
tmp_def = opt.default
if tmp_def == "":
tmp_def = '""'
line = line.format(opt.name, str(opt.types), opt.help, ', default=', tmp_def)
line = line.format(
opt.name,
str(opt.types),
opt.help,
', default=',
tmp_def)
except AttributeError: # no default value
line = line.format(opt.name, str(opt.types), opt.help, "", "")
print(line)
......@@ -212,7 +219,8 @@ class ConfigParser(object):
self[name].allowed_keys.append(key)
except AttributeError:
if type(dict()) not in self[name].types:
raise RuntimeError("Allowing a key makes sense for dictionaries only")
raise RuntimeError(
"Allowing a key makes sense for dictionaries only")
self[name].allowed_keys = [key]
self[name].allowed_keys.append(key)
......@@ -239,7 +247,7 @@ class ConfigParser(object):
# These hdlmake keys wont be inherited
key_purge_list = ["modules", "files", "include_dirs",
"inc_makefiles", "library"]
"inc_makefiles", "library"]
for key_to_be_deleted in key_purge_list:
extra_context.pop(key_to_be_deleted, None)
......@@ -254,12 +262,12 @@ class ConfigParser(object):
content = ''
content = self.arbitrary_code + '\n' + content
#now the trick:
#I take the arbitrary code and parse it
#the values are not important, but thanks to it I can check
#if a variable came from the arbitrary code.
#This is important because in the manifests only certain group
#of variables is allowed. In arbitrary code all of them can be used.
# now the trick:
# I take the arbitrary code and parse it
# the values are not important, but thanks to it I can check
# if a variable came from the arbitrary code.
# This is important because in the manifests only certain group
# of variables is allowed. In arbitrary code all of them can be used.
arbitrary_options = {}
import sys
try:
......@@ -273,7 +281,7 @@ class ConfigParser(object):
quit()
except:
logging.error("Unexpected error while parsing arbitrary code:")
print(str(sys.exc_info()[0])+':'+str(sys.exc_info()[1]))
print(str(sys.exc_info()[0]) + ':' + str(sys.exc_info()[1]))
quit()
try:
......@@ -281,16 +289,22 @@ class ConfigParser(object):
exec(content, extra_context, options)
printed = s.getvalue()
if len(printed) > 0:
logging.info("The manifest inside " + self.config_file + " tried to print something:")
logging.info(
"The manifest inside " +
self.config_file +
" tried to print something:")
for line in printed.split('\n'):
print("> " + line)
#print "out:", s.getvalue()
# print "out:", s.getvalue()
except SyntaxError as e:
logging.error("Invalid syntax in the manifest file " + self.config_file + ":\n" + str(e))
logging.error(
"Invalid syntax in the manifest file " + self.config_file + ":\n" + str(e))
logging.error(content)
quit()
except:
logging.error("Encountered unexpected error while parsing " + self.config_file)
logging.error(
"Encountered unexpected error while parsing " +
self.config_file)
logging.error(content)
print(str(sys.exc_info()[0]) + ':' + str(sys.exc_info()[1]))
raise
......@@ -303,18 +317,24 @@ class ConfigParser(object):
continue # finish processing of this variable here
else:
ret[opt_name] = val
logging.debug("New custom variable found: %s (=%s).\n" % (opt_name, val))
logging.debug(
"New custom variable found: %s (=%s).\n" %
(opt_name, val))
continue
opt = self[opt_name]
if type(val) not in opt.types:
raise RuntimeError("Given option: %s doesn't match specified types: %s" % (str(type(val)), str(opt.types)))
raise RuntimeError(
"Given option: %s doesn't match specified types: %s" %
(str(type(val)), str(opt.types)))
ret[opt_name] = val
# print("Opt_name ", opt_name)
if type(val) == type(dict()):
if isinstance(val, type(dict())):
try:
for key in val:
if key not in self[opt_name].allowed_keys:
raise RuntimeError("Encountered unallowed key: %s for option '%s'" % (key, opt_name))
raise RuntimeError(
"Encountered unallowed key: %s for option '%s'" %
(key, opt_name))
except AttributeError: # no allowed_keys member - don't perform any check
pass
......
......@@ -25,6 +25,7 @@ import os
import logging
import platform
def url_parse(url):
"""
Check if link to a repo seems to be correct. Filter revision number and branch
......@@ -78,10 +79,10 @@ def pathsplit(p, rest=None):
rest = []
(h, t) = os.path.split(p)
if len(h) < 1:
return [t]+rest
return [t] + rest
if len(t) < 1:
return [h]+rest
return pathsplit(h, [t]+rest)
return [h] + rest
return pathsplit(h, [t] + rest)
def commonpath(l1, l2, common=None):
......@@ -93,7 +94,7 @@ def commonpath(l1, l2, common=None):
return (common, l1, l2)
if l1[0] != l2[0]:
return (common, l1, l2)
return commonpath(l1[1:], l2[1:], common+[l1[0]])
return commonpath(l1[1:], l2[1:], common + [l1[0]])
def is_rel_path(path):
......@@ -158,9 +159,9 @@ def flatten_list(sth):
sth = []
return sth
def check_windows():
if platform.system() == 'Windows':
return True
else:
return False
......@@ -27,57 +27,57 @@ from __future__ import print_function
import os
__ALL__ = [ 'colored', 'cprint' ]
__ALL__ = ['colored', 'cprint']
VERSION = (1, 1, 0)
ATTRIBUTES = dict(
list(zip([
'bold',
'dark',
'',
'underline',
'blink',
'',
'reverse',
'concealed'
],
list(range(1, 9))
))
)
list(zip([
'bold',
'dark',
'',
'underline',
'blink',
'',
'reverse',
'concealed'
],
list(range(1, 9))
))
)
del ATTRIBUTES['']
HIGHLIGHTS = dict(
list(zip([
'on_grey',
'on_red',
'on_green',
'on_yellow',
'on_blue',
'on_magenta',
'on_cyan',
'on_white'
],
list(range(40, 48))
))
)
list(zip([
'on_grey',
'on_red',
'on_green',
'on_yellow',
'on_blue',
'on_magenta',
'on_cyan',
'on_white'
],
list(range(40, 48))
))
)
COLORS = dict(
list(zip([
'grey',
'red',
'green',
'yellow',
'blue',
'magenta',
'cyan',
'white',
],
list(range(30, 38))
))
)
list(zip([
'grey',
'red',
'green',
'yellow',
'blue',
'magenta',
'cyan',
'white',
],
list(range(30, 38))
))
)
RESET = '\033[0m'
......@@ -156,13 +156,12 @@ if __name__ == '__main__':
cprint('Reversed blue color', 'blue', attrs=['reverse'])
cprint('Concealed Magenta color', 'magenta', attrs=['concealed'])
cprint('Bold underline reverse cyan color', 'cyan',
attrs=['bold', 'underline', 'reverse'])
attrs=['bold', 'underline', 'reverse'])
cprint('Dark blink concealed white color', 'white',
attrs=['dark', 'blink', 'concealed'])
attrs=['dark', 'blink', 'concealed'])
print(('-' * 78))
print('Test mixing:')
cprint('Underline red on grey color', 'red', 'on_grey',
['underline'])
['underline'])
cprint('Reversed green on red color', 'green', 'on_red', ['reverse'])
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment