Commit f125d15f authored by Tristan Gingold's avatar Tristan Gingold

Add parsing of XCI files to locate Vivado IP module names.

From Nick Brereton
parent c4b5fced
......@@ -194,10 +194,13 @@ class VEOFile(File):
pass
class XCIFile(File):
class XCIFile(SourceFile):
"""Xilinx Core IP File"""
pass
def __init__(self, path, module, library=None):
SourceFile.__init__(self, path=path, module=module, library=library)
from hdlmake.xci_parser import XCIParser
self.parser = XCIParser(self)
XILINX_FILE_DICT = {
'xise': XISEFile,
......
......@@ -26,7 +26,8 @@
from __future__ import absolute_import
from .xilinx import ToolXilinx
from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile,
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile, BMMFile,
MIFFile, RAMFile, VHOFile, VEOFile, XCFFile)
......@@ -48,7 +49,6 @@ class ToolVivado(ToolXilinx):
SUPPORTED_FILES = {
XDCFile: ToolXilinx._XILINX_SOURCE,
XCFFile: ToolXilinx._XILINX_SOURCE,
XCIFile: ToolXilinx._XILINX_SOURCE,
NGCFile: ToolXilinx._XILINX_SOURCE,
XMPFile: ToolXilinx._XILINX_SOURCE,
XCOFile: ToolXilinx._XILINX_SOURCE,
......@@ -61,6 +61,12 @@ class ToolVivado(ToolXilinx):
VHOFile: ToolXilinx._XILINX_SOURCE,
VEOFile: ToolXilinx._XILINX_SOURCE}
HDL_FILES = {
VHDLFile: ToolXilinx._XILINX_SOURCE,
VerilogFile: ToolXilinx._XILINX_SOURCE,
SVFile: ToolXilinx._XILINX_SOURCE,
XCIFile: ToolXilinx._XILINX_SOURCE}
CLEAN_TARGETS = {'clean': [".Xil", "*.jou", "*.log", "*.pb", "*.dmp",
"$(PROJECT).cache", "$(PROJECT).data", "work",
"$(PROJECT).runs", "$(PROJECT).hw",
......@@ -79,3 +85,4 @@ class ToolVivado(ToolXilinx):
self._standard_libs.extend(ToolVivado.STANDARD_LIBS)
self._clean_targets.update(ToolVivado.CLEAN_TARGETS)
self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
self._hdl_files.update(ToolVivado.HDL_FILES)
#!/usr/bin/python
#
# Author: Nick Brereton
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see .
#
"""This module provides a Xilinx XCI IP description parser for HDLMake"""
from __future__ import absolute_import
import re
import logging
from xml.etree import ElementTree as ET
from .new_dep_solver import DepParser
from .dep_file import DepRelation
from hdlmake.srcfile import create_source_file
class XCIParser(DepParser):
"""Class providing the Xilinx XCI parser"""
def __init__(self, dep_file):
DepParser.__init__(self, dep_file)
def parse(self, dep_file):
"""Parse a Xilinx XCI IP description file to determine the provided module(s)"""
if dep_file.is_parsed:
return
logging.debug("Parsing %s", dep_file.path)
with open(dep_file.path) as f:
# extract namespaces with a regex -- not really ideal, but without pulling in
# an external xml lib I can't think of a better way.
xmlnsre = re.compile(r'''\bxmlns:(\w+)\s*=\s*"(\w+://[^"]*)"''', re.MULTILINE)
xml = f.read()
nsmap = dict(xmlnsre.findall(xml))
value = ET.fromstring(xml).find('spirit:componentInstances/spirit:componentInstance/spirit:instanceName', nsmap)
if not value is None:
modulename = value.text
logging.debug("found module %s.%s", dep_file.library, modulename)
dep_file.add_relation(
DepRelation("%s.%s" % (dep_file.library, modulename),
DepRelation.PROVIDE, DepRelation.MODULE))
dep_file.is_parsed = True
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