Commit eefea3f0 authored by Tristan Gingold's avatar Tristan Gingold

Add tests.

parent cb77d7df
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
TOP_MODULE := gate3_tb
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := /home/tgingold/Repositories/ohwr/hdl-make/vhdl/hdp/lin64
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := ../files/gate3_tb.v \
VERILOG_OBJ := work/gate3_tb/.gate3_tb_v \
VHDL_SRC := ../files/gate.vhdl \
../files/gate3.vhd \
VHDL_OBJ := work/gate/.gate_vhdl \
work/gate3/.gate3_vhd \
LIBS := work
LIB_IND := work/.work
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
cp $< .
fuse:
fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
work/.work:
(mkdir -p work && touch work/.work && echo work=work >> xilinxsim.ini) || rm -rf work
work/gate3_tb/.gate3_tb_v: ../files/gate3_tb.v ../files/gate3.vhd
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../files $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate_vhdl: ../files/gate.vhdl work/gate/.gate
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate:
@mkdir -p $(dir $@) && touch $@
work/gate3/.gate3_vhd: ../files/gate3.vhd work/gate3/.gate3
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gate3/.gate3: \
work/gate/.gate_vhdl
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb isim_proj isim_proj.*
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="isim"
sim_path="not_to_be_found"
top_module = "gate3_tb"
files = [ "../files/gate3.vhd", "../files/gate.vhdl", "../files/gate3_tb.v" ]
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
......@@ -65,6 +65,10 @@ def test_makefile_003():
def test_makefile_004():
run_compare(path="004msim")
def test_filename_opt():
run(['-f', 'my.mk'], path="062filename_opt")
os.remove("062filename_opt/my.mk")
def test_fetch():
run(['fetch'], path="001ise")
......@@ -247,6 +251,10 @@ def test_no_syn_tool():
def test_no_files():
run([], path="042nofiles")
def test_no_bin():
with Config(path="061err_nobin", fakebin="no_fakebin") as _:
hdlmake.__main__.hdlmake([])
def test_local043():
run_compare(path="043local_fetch")
......
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