Commit edf264a1 authored by Phil Clarke's avatar Phil Clarke Committed by Tristan Gingold

Add VHDL library and PolarfireSOC device example to LiberoSOC in hdlmake

parent e9637ef9
......@@ -27,7 +27,11 @@
from __future__ import absolute_import
from .makefilesyn import MakefileSyn
from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile, CXFFile
from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile, CXFFile, SourceFile
from ..util import shell
import logging
class ToolLiberoSoC(MakefileSyn):
......@@ -44,6 +48,7 @@ class ToolLiberoSoC(MakefileSyn):
STANDARD_LIBS = ['ieee', 'std']
_LIBERO_SOURCE = 'create_links {0} {{srcfile}}'
_LIBERO_LIB = 'add_file_to_library -library {{library}} -file {{srcfile}}'
SUPPORTED_FILES = {
SDCFile: _LIBERO_SOURCE.format('-sdc'),
......@@ -54,9 +59,17 @@ class ToolLiberoSoC(MakefileSyn):
VerilogFile: _LIBERO_SOURCE.format('-hdl_source'),
CXFFile: ''}
CLEAN_TARGETS = {'clean': ["$(PROJECT)"],
HDL_LIBRARIES = {
VHDLFile: _LIBERO_LIB.format(),
VerilogFile: _LIBERO_LIB.format()
}
CLEAN_TARGETS = {'clean': ["$(PROJECT)", "*.log"],
'mrproper': ["*.pdb", "*.stp"]}
TCL_CONTROLS = {
'create': 'new_project -location {{./{0}}} '
'-name {{{0}}} -hdl {{{1}}} '
......@@ -68,22 +81,10 @@ class ToolLiberoSoC(MakefileSyn):
'project': '$(TCL_CREATE)\n'
'source files.tcl\n'
'refresh\n'
'set_root $(TOP_MODULE)\n'
'{0}\n'
'$(TCL_SAVE)\n'
'$(TCL_CLOSE)',
'bitstream': '$(TCL_OPEN)\n'
'run_tool -name {GENERATEPROGRAMMINGDATA}\n'
'file mkdir ./$(PROJECT)/bitstream\n'
'export_bitstream_file '
'-file_name {$(PROJECT)} '
'-export_dir {$(PROJECT)/bitstream} '
'-format {STP} -trusted_facility_file 1 '
'-trusted_facility_file_components {FABRIC} '
'-serialization_stapl_type {SINGLE} '
'-serialization_target_solution {FLASHPRO_3_4_5}\n'
'$(TCL_SAVE)\n'
'$(TCL_CLOSE)',
'bitstream': ' Device not supported, so no bitstream for now!',
'install_source': '$(PROJECT)/designer/impl1/$(SYN_TOP).pdb'}
# Override the build command, because no space is expected between TCL_INTERPRETER and the tcl file
......@@ -93,15 +94,93 @@ class ToolLiberoSoC(MakefileSyn):
{0}: {1} {0}.tcl
\t$(SYN_PRE_{2}_CMD)
\t$(TCL_INTERPRETER)$@.tcl
\t$(TCL_INTERPRETER)$@.tcl LOGFILE:{0}_output.log
\t$(SYN_POST_{2}_CMD)
\t{4} $@
"""
_BITSTREAM_POLARFIRESOC = "$(TCL_OPEN)\n"\
+ "run_tool -name {GENERATEPROGRAMMINGDATA}\n" \
+ "file mkdir ./$(PROJECT)/bitstream\n" \
+ "export_bitstream_file "\
+ "-file_name {$(PROJECT)} "\
+ "-export_dir {$(PROJECT)/bitstream} "\
+ "-format {STP} -trusted_facility_file 1 "\
+ "-trusted_facility_file_components {FABRIC} \n"\
+ "$(TCL_SAVE)\n"\
+ "$(TCL_CLOSE)"
_BITSTREAM_IGLOO2 = "$(TCL_OPEN)\n"\
+ "run_tool -name {GENERATEPROGRAMMINGDATA}\n" \
+ "file mkdir ./$(PROJECT)/bitstream\n" \
+ "export_bitstream_file "\
+ "-file_name {$(PROJECT)} "\
+ "-export_dir {$(PROJECT)/bitstream} "\
+ "-format {STP} -trusted_facility_file 1 "\
+ "-trusted_facility_file_components {FABRIC} "\
+ "-serialization_stapl_type {SINGLE} "\
+ "-serialization_target_solution {FLASHPRO_3_4_5}\n"\
+ "$(TCL_SAVE)\n"\
+ "$(TCL_CLOSE)"
def __init__(self):
super(ToolLiberoSoC, self).__init__()
self._tcl_controls.update(ToolLiberoSoC.TCL_CONTROLS)
def _makefile_syn_files_predefinelibs(self):
"""create libraries before adding files to the files.tcl file"""
libraries = self.get_all_libs()
if len(libraries) > 1:
for libname in libraries:
self.writeln('\t\t@echo add_library -library ' + libname + ' >> $@')
# PROBABLY NAUGHTY: as at this point we know what the device type is; let's also adjust the
# TCL_CONTROLS[bitstream] so it is device appropriate
# shouldl this really be done in : _makefile_syn_top??
syn_family = self.manifest_dict.get("syn_family", '')
#logging.info(self.TOOL_INFO['name'] + " _makefile_syn_files_predefinelibs got family_name as:" + syn_family)
if syn_family == "PolarFireSoC":
self._tcl_controls['bitstream'] = self._BITSTREAM_POLARFIRESOC
#logging.info(self.TOOL_INFO['name'] + " set GENERATEPROGRAMMINGDATA for PolarfireSoc.")
elif syn_family == "IGLOO2":
self._tcl_controls['bitstream'] = self._BITSTREAM_IGLOO2
#logging.info(self.TOOL_INFO['name'] + " set GENERATEPROGRAMMINGDATA for IGLOO2.")
else:
logging.info(self.TOOL_INFO['name'] + "TODO: Somebody needs to add device support for this family, PolarFireSoC and IGLOO2 are supported. Can you do it?")
def _makefile_syn_files_map_files_to_lib(self):
"""map specific files to specific libraries when it has to be a separate command"""
fileset_dict = {}
fileset_dict.update(self.HDL_LIBRARIES)
libraries = self.get_all_libs()
if len(libraries) > 1:
for srcfile in self.fileset.sort():
command = fileset_dict.get(type(srcfile))
# Put the file in files.tcl only if it is supported.
#logging.info(self.TOOL_INFO['name'] + " looping")
if command is not None:
# Libraries are defined only for hdl files.
if isinstance(srcfile, SourceFile):
library = srcfile.library
else:
library = None
command = command.format(srcfile=shell.tclpath(srcfile.rel_path()),
library=library)
command = '\t\techo "{}" >> $@'.format(command)
if shell.check_windows_commands():
command = command.replace('"', '')
self.writeln(command)
def _makefile_syn_tcl(self):
"""Create a Libero synthesis project by TCL"""
syn_project = self.manifest_dict["syn_project"]
......@@ -123,14 +202,26 @@ class ToolLiberoSoC(MakefileSyn):
syn_package.upper(),
syn_grade)
project_tmp = self._tcl_controls["project"]
synthesis_constraints = []
synthesis_constraints = []
compilation_constraints = []
timing_constraints = []
ret = []
library_for_top_module = str(self.get_library_for_top_module())
libraries = self.get_all_libs()
if len(libraries) > 1:
line = 'set_root -module {$(TOP_MODULE)::' + library_for_top_module + '}'
else:
line = 'set_root -module {$(TOP_MODULE)}'
ret.append(line)
# First stage: linking files
for file_aux in self.fileset.sort():
if isinstance(file_aux, SDCFile):
synthesis_constraints.append(file_aux)
compilation_constraints.append(file_aux)
timing_constraints.append(file_aux)
elif isinstance(file_aux, PDCFile):
compilation_constraints.append(file_aux)
# Second stage: Organizing / activating synthesis constraints (the top
......@@ -140,7 +231,7 @@ class ToolLiberoSoC(MakefileSyn):
for file_aux in synthesis_constraints:
line = line + '-file {' + file_aux.rel_path() + '} '
line = line + \
'-module {$(TOP_MODULE)::work} -input_type {constraint} '
'-module {$(TOP_MODULE)::' + library_for_top_module + '} -input_type {constraint} '
ret.append(line)
# Third stage: Organizing / activating compilation constraints (the top
# module needs to be present!)
......@@ -149,10 +240,17 @@ class ToolLiberoSoC(MakefileSyn):
for file_aux in compilation_constraints:
line = line + '-file {' + file_aux.rel_path() + '} '
line = line + \
'-module {$(TOP_MODULE)::work} -input_type {constraint} '
'-module {$(TOP_MODULE)::' + library_for_top_module + '} -input_type {constraint} '
ret.append(line)
# Fourth stage: set root/top module
line = 'set_root -module {$(TOP_MODULE)::work}'
ret.append(line)
# is this device dependant?
if timing_constraints:
line = 'organize_tool_files -tool {VERIFYTIMING} '
for file_aux in timing_constraints:
line = line + '-file {' + file_aux.rel_path() + '} '
line = line + \
'-module {$(TOP_MODULE)::' + library_for_top_module + '} -input_type {constraint} '
ret.append(line)
self._tcl_controls['project'] = project_tmp.format('\n'.join(ret))
super(ToolLiberoSoC, self)._makefile_syn_tcl()
......@@ -225,3 +225,32 @@ SYN_POST_{0}_CMD := {2}
def get_num_hdl_libs(self):
num_libs = len(self.get_all_libs());
return num_libs;
def get_library_for_top_module(self):
if self.get_num_hdl_libs() == 1:
# this may now be excessive, based on the "catch-all" return statement at the bottom.
return self.default_library
else:
#find and return the library name for the top HDL module...
fileset_dict = {}
fileset_dict.update(self.HDL_FILES)
top_file = self.manifest_dict["syn_top"]
for hdlfiletype in fileset_dict:
for specific_file in self.fileset:
if isinstance(specific_file, hdlfiletype):
if specific_file.purename == top_file:
#logging.info(self.TOOL_INFO['name']
# + "libfinder_top_module, FOUND library_name: "
# + specific_file.library + " for module: "
# + top_file )
return str(specific_file.library)
#In case we dont find a library then post an info message before returning the default value
logging.info( self.TOOL_INFO['name']
+ "function get_library_for_top_module, "
+ "failed to find a library for the top module: "
+ top_file + " Will use the default_library: "
+ self.default_library
)
return self.default_library
......@@ -4,7 +4,7 @@ action = "synthesis"
language = "verilog"
syn_family = "IGLOO2"
syn_device = "M2GL060"
syn_device = "M2GL025"
syn_grade = "-1"
syn_package = "484 FBGA"
syn_top = "igloo2_top"
......
......@@ -4,7 +4,7 @@ action = "synthesis"
language = "vhdl"
syn_family = "IGLOO2"
syn_device = "M2GL060"
syn_device = "M2GL025"
syn_grade = "-1"
syn_package = "484 FBGA"
syn_top = "igloo2_top"
......
target = "microsemi"
action = "synthesis"
syn_family = "PolarFireSoC"
syn_device = "MPFS250T_ES"
syn_grade = ""
syn_package = "FCVG484"
syn_top = "polarfiresoc_top"
syn_project = "test"
syn_tool = "liberosoc"
modules = {
"local" : [ "../../../top/polarfire_sk/vhdl" ],
}
......@@ -4,11 +4,12 @@
#
# IO banks setting
#
set_iobank Bank2 -vcci 3.3 -fixed yes
set_iobank Bank4 -vcci 3.3 -fixed no
set_iobank Bank5 -vcci 3.3 -fixed yes
set_iobank Bank6 -vcci 3.3 -fixed yes
set_iobank Bank9 -vcci 3.3 -fixed yes
# Bank default bank voltage assignments commented out for Libero 2021.1 Silver
#set_iobank Bank2 -vcci 3.3 -fixed yes
#set_iobank Bank4 -vcci 3.3 -fixed no
#set_iobank Bank5 -vcci 3.3 -fixed yes
#set_iobank Bank6 -vcci 3.3 -fixed yes
#set_iobank Bank9 -vcci 3.3 -fixed yes
#
# I/O constraints
......
# Microsemi Physical design constraints file
# Family: ProASIC3 , Die: A3P250 , Package: 208 PQFP , Speed grade: -2
##
## IO banks setting
##
#
#set_iobank Bank2 -vcci 3.30 -fixed no
#set_iobank Bank1 -vcci 3.30 -fixed no
#set_iobank Bank0 -vcci 3.30 -fixed no
#
##
## I/O constraints
##
#
set_io -port_name clear_i -pin_name AB12 -fixed true -DIRECTION INPUT
set_io -port_name clock_i -pin_name AB14 -fixed true -DIRECTION INPUT
set_io -port_name count_i -pin_name AB13 -fixed true -DIRECTION INPUT
set_io -port_name {led_o[0]} -pin_name AA12 -fixed true -DIRECTION OUTPUT
set_io -port_name {led_o[1]} -pin_name AA13 -fixed true -DIRECTION OUTPUT
set_io -port_name {led_o[2]} -pin_name AA15 -fixed true -DIRECTION OUTPUT
set_io -port_name {led_o[3]} -pin_name AA16 -fixed true -DIRECTION OUTPUT
set_io -port_name {led_o[4]} -pin_name AA17 -fixed true -DIRECTION OUTPUT
set_io -port_name {led_o[5]} -pin_name AA18 -fixed true -DIRECTION OUTPUT
set_io -port_name {led_o[6]} -pin_name AA20 -fixed true -DIRECTION OUTPUT
set_io -port_name {led_o[7]} -pin_name AA21 -fixed true -DIRECTION OUTPUT
\ No newline at end of file
# Top Level Design Parameters
# Clocks
create_clock -name {clk} -period 10 [get_ports {clock_i}]
files = [
"polarfiresoc_top.vhd",
"../polarfiresoc_top.pdc",
"../polarfiresoc_top.sdc",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, Microsemi ProASIC3 Starter Kit
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity polarfiresoc_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end polarfiresoc_top;
-----------------------------------------------------------------------
architecture structure of polarfiresoc_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= clear_i;
s_count <= count_i;
led_o <= s_Q;
end architecture structure;
----------------------------------------------------------------
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := repinned_top
PROJECT := demo
PROJECT_FILE := $(PROJECT).prjx
TOOL_PATH :=
TCL_INTERPRETER := libero SCRIPT:
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := IGLOO2
SYN_DEVICE := M2GL025
SYN_PACKAGE := 484 FBGA
SYN_GRADE := -1
TCL_CREATE := new_project -location {./demo} -name {demo} -hdl {VHDL} -family {IGLOO2} -die {M2GL025} -package {484 FBGA} -speed {-1}
TCL_OPEN := open_project -file {$(PROJECT)/$(PROJECT_FILE)}
TCL_SAVE := save_project
TCL_CLOSE := close_project
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
files.tcl:
@echo add_library -library lib_a >> $@
@echo add_library -library lib_b >> $@
@echo add_library -library lib_c >> $@
echo "create_links -hdl_source rtl/lib_a/axi_regs_a.vhd" >> $@
echo "create_links -hdl_source rtl/lib_a/register_access_fns_pkg.vhd" >> $@
echo "create_links -hdl_source rtl/lib_a/register_types_pkg.vhd" >> $@
echo "create_links -hdl_source rtl/lib_b/axi_regs_b.vhd" >> $@
echo "create_links -hdl_source rtl/lib_b/register_access_fns_pkg.vhd" >> $@
echo "create_links -hdl_source rtl/lib_b/register_types_pkg.vhd" >> $@
echo "create_links -hdl_source rtl/lib_c/merged_top.vhd" >> $@
echo "create_links -hdl_source rtl/lib_c/repinned_top.vhd" >> $@
echo "add_file_to_library -library lib_a -file rtl/lib_a/axi_regs_a.vhd" >> $@
echo "add_file_to_library -library lib_a -file rtl/lib_a/register_access_fns_pkg.vhd" >> $@
echo "add_file_to_library -library lib_a -file rtl/lib_a/register_types_pkg.vhd" >> $@
echo "add_file_to_library -library lib_b -file rtl/lib_b/axi_regs_b.vhd" >> $@
echo "add_file_to_library -library lib_b -file rtl/lib_b/register_access_fns_pkg.vhd" >> $@
echo "add_file_to_library -library lib_b -file rtl/lib_b/register_types_pkg.vhd" >> $@
echo "add_file_to_library -library lib_c -file rtl/lib_c/merged_top.vhd" >> $@
echo "add_file_to_library -library lib_c -file rtl/lib_c/repinned_top.vhd" >> $@
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo source files.tcl >> $@
echo refresh >> $@
echo set_root -module {$(TOP_MODULE)::lib_c} >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)$@.tcl LOGFILE:project_output.log
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo run_tool -name {GENERATEPROGRAMMINGDATA} >> $@
echo file mkdir ./$(PROJECT)/bitstream >> $@
echo export_bitstream_file -file_name {$(PROJECT)} -export_dir {$(PROJECT)/bitstream} -format {STP} -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} -serialization_stapl_type {SINGLE} -serialization_target_solution {FLASHPRO_3_4_5} >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)$@.tcl LOGFILE:bitstream_output.log
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) $(PROJECT) *.log
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.pdb *.stp
.PHONY: mrproper clean all
target = "microsemi"
action = "synthesis"
syn_tool = "liberosoc"
syn_family = "IGLOO2"
syn_device = "M2GL025"
syn_grade = "-1"
syn_package = "484 FBGA"
syn_top = "repinned_top"
syn_project = "demo"
modules = {
"local" : [ "rtl/lib_c" ],
}
files = [
"register_types_pkg.vhd",
"register_access_fns_pkg.vhd",
"axi_regs_a.vhd",
]
library = "lib_a"
-- Copyright Philip Clarke 2020 - 2021
--
-- ---------------------------------------------------------------------
-- This source describes Open Hardware and is licensed under the CERN-OHL-S v2.
-- You may redistribute and modify this source and make products using it
-- under the terms of the CERN-OHL-S v2 (https://ohwr.org/cern_ohl_s_v2.txt).
--
-- This source is distributed WITHOUT ANY EXPRESS OR IMPLIED
-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see
-- the CERN-OHL-S v2 for applicable conditions.
--
-- Source location: https://github.com/hdlved/vhdl2008_testcases
--
-- As per CERN-OHL-S v2 section 4, should hardware be produced using this source,
-- the product must visibly display the source location in its documentation,
--
-- -----------------------------------------------------------------------------
--
-- This code is probably available to purchase from the orgional author under a
-- different license if that suits your project better.
--
-- -----------------------------------------------------------------------------
-- This VHDL entity implements a basic pipeline stage with behaviour that matches:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.register_types_pkg.all;
use work.register_access_fns_pkg.all;
entity axi_regs_a is
generic (
g_AXI_Ax_ADDR_W : positive;
g_DAT_BW : positive -- W channel (Data and strobe width control) -- Byte Width
-- & also R channel
);
port (
clk : in std_logic;
rst_n : in std_logic; -- sync reset
aw_ready : out std_logic;
aw_valid : in std_logic;
aw_addr : in std_logic_vector( g_AXI_Ax_ADDR_W-1 downto 0); ----- TODO: THIS should be a BYTE_ADDR not WORD ADDR
aw_prot : in std_logic_vector( 2 downto 0);
-- write data port
w_ready : out std_logic;
w_valid : in std_logic;
w_data : in std_logic_vector(g_DAT_BW*8 -1 downto 0);
w_strb : in std_logic_vector(g_DAT_BW -1 downto 0);
-- write response port
b_ready : in std_logic;
b_valid : out std_logic;
b_resp : out std_logic_vector(1 downto 0);
-- read address port
ar_ready : out std_logic;
ar_valid : in std_logic;
ar_addr : in std_logic_vector(g_AXI_Ax_ADDR_W-1 downto 0); ----- TODO: THIS should be a BYTE_ADDR not WORD ADDR
ar_prot : in std_logic_vector( 2 downto 0);
-- read response port
r_ready : in std_logic;
r_valid : out std_logic;
r_data : out std_logic_vector(g_DAT_BW*8 - 1 downto 0);
r_resp : out std_logic_vector( 1 downto 0);
--------------------------------------------------------------------------
regs_out : out t_regs_out;
regs_in : in t_regs_in
);
end entity axi_regs_a;
architecture rtl of axi_regs_a is
signal do_write_this_cycle : std_logic;
signal do_read_this_cycle : std_logic;
signal wr_regs_int : t_regs_out;
signal int_r_valid : std_logic;
signal b_valid_int : std_logic;
begin
regs_out <= wr_regs_int;
do_read_this_cycle <= r_ready and ar_valid and not int_r_valid;
ar_ready <= do_read_this_cycle;
r_valid <= int_r_valid;
proc_read : process (clk)
variable v_bad_addr : boolean;
variable v_prot_err : boolean;
variable v_rd_val : std_logic_vector(r_data'range);
variable v_good_addr : boolean;
begin
if rising_edge(clk) then
if int_r_valid = '1' and r_ready = '1' then
int_r_valid <= '0';
end if;
if do_read_this_cycle = '1' then
r_resp <= "00"; -- == OKAY
v_good_addr := false;
for byteno in 0 to g_DAT_BW-1 loop
p_read_byte( byte_addr => to_integer(unsigned(ar_addr) + byteno),
rd_prot => ar_prot,
regs_out => wr_regs_int,
regs_in => regs_in,
bad_rd_addr => v_bad_addr,
rd_prot_err => v_prot_err,
rd_byte => v_rd_val((byteno + 1) * 8 -1 downto byteno * 8)
);
if v_prot_err then
r_resp <= "11"; -- == EXOKAY (OK ,I am not doing exclusice accesses and this is a bodge to not strip out the signal..
end if;
if not v_bad_addr then
v_good_addr := true;
end if;
end loop;
if not v_good_addr then
r_resp <= "10"; -- == slv_err
end if;
r_data <= v_rd_val;
int_r_valid <= '1';
end if;
if rst_n = '0' then
int_r_valid <= '0';
end if;
end if;
end process;
do_write_this_cycle <= aw_valid and w_valid and b_ready and not b_valid_int;
w_ready <= do_write_this_cycle;
aw_ready <= do_write_this_cycle;
b_valid <= b_valid_int;
proc_write : process (clk)
variable v_bad_addr : boolean;
variable v_prot_err : boolean;
variable v_good_addr : boolean;
variable v_prot_err_word : boolean;
begin
if rising_edge(clk) then
p_do_wc(wr_regs_int);
if b_valid_int = '1' and b_ready = '1' then
b_valid_int <= '0';
end if;
if do_write_this_cycle = '1' then
b_resp <= "00";
b_valid_int <= '1';
v_good_addr := false;
v_prot_err_word := false;
for byteno in 0 to g_DAT_BW-1 loop
if w_strb(byteno) = '1' then
p_write_byte(
byte_addr => to_integer(unsigned(aw_addr) + byteno), -- assumes aw_Addr is always word aligned...
wr_prot => aw_prot,
wr_byte => w_data((byteno*8) + 7 downto (byteno*8)),
regs_out => wr_regs_int,
bad_wr_addr => v_bad_addr,
wr_prot_err => v_prot_err
);
if not v_bad_addr then
v_good_addr := true;
end if;