Add VHDL and Verilog template files support to Vivado

parent 92c32a9f
......@@ -182,6 +182,16 @@ class RAMFile(File):
pass
class VHOFile(File):
"""Xilinx VHDL Template File"""
pass
class VEOFile(File):
"""Xilinx Verilog Template File"""
pass
class XCIFile(File):
"""Xilinx Core IP File"""
pass
......@@ -202,6 +212,8 @@ XILINX_FILE_DICT = {
'coe': COEFile,
'mif': MIFFile,
'ram': RAMFile,
'vho': VHOFile,
'veo': VEOFile,
'xci': XCIFile}
......
......@@ -29,7 +29,7 @@ from .xilinx import ToolXilinx
from .make_sim import ToolSim
from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile,
MIFFile, RAMFile)
MIFFile, RAMFile, VHOFile, VEOFile)
class ToolVivado(ToolXilinx, ToolSim):
......@@ -48,7 +48,7 @@ class ToolVivado(ToolXilinx, ToolSim):
SUPPORTED_FILES = [XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile,
MIFFile, RAMFile]
MIFFile, RAMFile, VHOFile, VEOFile]
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
"$(PROJECT).cache", "$(PROJECT).data", "work",
......
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