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dd4824e9
Commit
dd4824e9
authored
Sep 19, 2019
by
Tristan Gingold
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Do not generate PWD assignment in Makefiles. Update baselines.
parent
cd9088c2
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45 changed files
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0 additions
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45 deletions
+0
-45
isim.py
hdlmake/tools/isim.py
+0
-1
make_sim.py
hdlmake/tools/make_sim.py
+0
-1
make_syn.py
hdlmake/tools/make_syn.py
+0
-1
Makefile.ref
testsuite/001ise/Makefile.ref
+0
-1
Makefile.ref
testsuite/002msim/Makefile.ref
+0
-1
Makefile.ref
testsuite/003msim/Makefile.ref
+0
-1
Makefile.ref
testsuite/004msim/Makefile.ref
+0
-1
Makefile.ref
testsuite/006ahdl/Makefile.ref
+0
-1
Makefile.ref
testsuite/007diamond/Makefile.ref
+0
-1
Makefile.ref
testsuite/008ghdl/Makefile.ref
+0
-1
Makefile.ref
testsuite/009icestorm/Makefile.ref
+0
-1
Makefile.ref
testsuite/010isim/Makefile.ref
+0
-1
Makefile
testsuite/011xfail/Makefile
+0
-1
Makefile.ref
testsuite/011xfail/Makefile.ref
+0
-1
Makefile.ref
testsuite/012icarus/Makefile.ref
+0
-1
Makefile.ref
testsuite/013libero/Makefile.ref
+0
-1
Makefile.ref
testsuite/014planahead/Makefile.ref
+0
-1
Makefile.ref
testsuite/015quartus/Makefile.ref
+0
-1
Makefile.ref
testsuite/016quartus_nofam/Makefile.ref
+0
-1
Makefile.ref
testsuite/017riviera/Makefile.ref
+0
-1
Makefile.ref
testsuite/018vivado/Makefile.ref
+0
-1
Makefile.ref
testsuite/019vsim/Makefile.ref
+0
-1
Makefile.ref
testsuite/023xci/Makefile.ref
+0
-1
Makefile.ref
testsuite/024vlog_parser/Makefile.ref
+0
-1
Makefile.ref
testsuite/025vlog_parser/Makefile.ref
+0
-1
Makefile.ref
testsuite/027vhdl_parser/Makefile.ref
+0
-1
Makefile
testsuite/032manifest_vars/Makefile
+0
-1
Makefile.ref
testsuite/033quartus/Makefile.ref
+0
-1
Makefile
testsuite/034quartus_prop/Makefile
+0
-1
Makefile.ref
testsuite/034quartus_prop/Makefile.ref
+0
-1
Makefile.ref
testsuite/040srcfiles/Makefile.ref
+0
-1
Makefile.ref
testsuite/043local_fetch/Makefile.ref
+0
-1
Makefile.ref
testsuite/044files_dir/Makefile.ref
+0
-1
Makefile.ref
testsuite/045incl_makefile/Makefile.ref
+0
-1
Makefile.ref
testsuite/046incl_makefiles/Makefile.ref
+0
-1
Makefile.ref
testsuite/052svlog_parser/Makefile.ref
+0
-1
Makefile.ref
testsuite/054vivado_props/Makefile.ref
+0
-1
Makefile.ref
testsuite/057msim_windows/Makefile.ref
+0
-1
Makefile.ref
testsuite/060isim_windows/Makefile.ref
+0
-1
Makefile.ref
testsuite/061err_nobin/Makefile.ref
+0
-1
Makefile.ref
testsuite/070err_syntop/Makefile.ref
+0
-1
Makefile.ref
testsuite/071ise_windows/Makefile.ref
+0
-1
Makefile.ref
testsuite/076extra_modules/Makefile.ref
+0
-1
Makefile.ref
testsuite/079err_vlg_macro/Makefile.ref
+0
-1
Makefile.ref
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
+0
-1
No files found.
hdlmake/tools/isim.py
View file @
dd4824e9
...
...
@@ -87,7 +87,6 @@ class ToolISim(ToolSim):
# Ensure the path is absolute and normalized
return
os
.
path
.
abspath
(
xilinx_ini_path
)
self
.
writeln
(
"""## variables #############################
PWD := $(shell pwd)
TOP_MODULE := """
+
self
.
manifest_dict
.
get
(
"sim_top"
,
''
)
+
"""
FUSE_OUTPUT ?= isim_proj
...
...
hdlmake/tools/make_sim.py
View file @
dd4824e9
...
...
@@ -44,7 +44,6 @@ class ToolSim(ToolMakefile):
"""Generic method to write the simulation Makefile top section"""
top_parameter
=
"""
\
TOP_MODULE := {top_module}
PWD := $(shell pwd)
"""
self
.
writeln
(
top_parameter
.
format
(
top_module
=
self
.
manifest_dict
[
"sim_top"
]))
...
...
hdlmake/tools/make_syn.py
View file @
dd4824e9
...
...
@@ -54,7 +54,6 @@ class ToolSyn(ToolMakefile):
tcl_interpreter
=
self
.
_tool_info
[
"linux_bin"
]
top_parameter
=
"""
\
TOP_MODULE := {top_module}
PWD := $(shell pwd)
PROJECT := {project_name}
PROJECT_FILE := $(PROJECT).{project_ext}
TOOL_PATH := {tool_path}
...
...
testsuite/001ise/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
...
...
testsuite/002msim/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/003msim/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
my_ini
...
...
testsuite/004msim/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
fake_bin/..
...
...
testsuite/006ahdl/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
...
...
testsuite/007diamond/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.ldf
TOOL_PATH
:=
...
...
testsuite/008ghdl/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate3
PWD
:=
$(
shell
pwd
)
GHDL
:=
ghdl
GHDL_OPT
:=
...
...
testsuite/009icestorm/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate2
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate2
PROJECT_FILE
:=
$(PROJECT)
.
TCL_INTERPRETER
:=
yosys
-c
...
...
testsuite/010isim/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
## variables #############################
PWD
:=
$(
shell
pwd
)
TOP_MODULE
:=
gate3_tb
FUSE_OUTPUT
?=
isim_proj
...
...
testsuite/011xfail/Makefile
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
...
...
testsuite/011xfail/Makefile.ref
View file @
dd4824e9
...
...
@@ -6,7 +6,6 @@
extra_line
:
makefile differs...
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
...
...
testsuite/012icarus/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate2
PWD
:=
$(
shell
pwd
)
IVERILOG_OPT
:=
...
...
testsuite/013libero/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.prjx
TOOL_PATH
:=
...
...
testsuite/014planahead/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.ppr
TOOL_PATH
:=
...
...
testsuite/015quartus/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
...
...
testsuite/016quartus_nofam/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
...
...
testsuite/017riviera/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
VCOM_FLAGS
:=
-quiet
-2008
...
...
testsuite/018vivado/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xpr
TOOL_PATH
:=
...
...
testsuite/019vsim/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
...
...
testsuite/023xci/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xpr
TOOL_PATH
:=
...
...
testsuite/024vlog_parser/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/025vlog_parser/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/027vhdl_parser/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/032manifest_vars/Makefile
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/033quartus/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
...
...
testsuite/034quartus_prop/Makefile
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
...
...
testsuite/034quartus_prop/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
...
...
testsuite/040srcfiles/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
mod2
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
...
...
testsuite/043local_fetch/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/044files_dir/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/045incl_makefile/Makefile.ref
View file @
dd4824e9
...
...
@@ -6,7 +6,6 @@
include
.
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/046incl_makefiles/Makefile.ref
View file @
dd4824e9
...
...
@@ -7,7 +7,6 @@ include a.mk
include
b.mk
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/052svlog_parser/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/054vivado_props/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xpr
TOOL_PATH
:=
...
...
testsuite/057msim_windows/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
..
...
...
testsuite/060isim_windows/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
## variables #############################
PWD
:=
$(
shell
pwd
)
TOP_MODULE
:=
gate3_tb
FUSE_OUTPUT
?=
isim_proj
...
...
testsuite/061err_nobin/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
## variables #############################
PWD
:=
$(
shell
pwd
)
TOP_MODULE
:=
gate3_tb
FUSE_OUTPUT
?=
isim_proj
...
...
testsuite/070err_syntop/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
None
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
...
...
testsuite/071ise_windows/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
...
...
testsuite/076extra_modules/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate_tb
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/079err_vlg_macro/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
View file @
dd4824e9
...
...
@@ -4,7 +4,6 @@
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
...
...
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