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d82dc290
Commit
d82dc290
authored
Nov 13, 2014
by
Adrian Fiergolski
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Plain Diff
Fix bug 1028.
Fix bugs in test files.
parent
e42a630a
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7 changed files
with
11 additions
and
22 deletions
+11
-22
vhdl_parser.py
hdlmake/vhdl_parser.py
+4
-8
RTLTopModuleSV.sv
tests/questa_uvm_sv/rtl/RTLTopModuleSV.sv
+1
-1
RTLTopModuleVHDL.vhdl
tests/questa_uvm_sv/rtl/RTLTopModuleVHDL.vhdl
+4
-9
includeModuleAVHDL.vhdl
tests/questa_uvm_sv/rtl/include/includeModuleAVHDL.vhdl
+0
-1
includeModuleBVHDL.vhdl
tests/questa_uvm_sv/rtl/include/includeModuleBVHDL.vhdl
+0
-1
includeModuleVHDL.vhdl
tests/questa_uvm_sv/rtl/include/includeModuleVHDL.vhdl
+0
-1
Makefile
tests/questa_uvm_sv/sim/tests/Makefile
+2
-1
No files found.
hdlmake/vhdl_parser.py
View file @
d82dc290
...
...
@@ -100,7 +100,7 @@ class VHDLParser(DepParser):
else
:
prev_is_gap
=
False
buf2
+=
c
.
lower
()
if
c
==
";"
:
if
(
c
==
";"
or
buf2
[
-
8
:]
==
"generate"
)
:
lines
.
append
(
buf2
)
buf2
=
""
else
:
...
...
@@ -110,16 +110,15 @@ class VHDLParser(DepParser):
patterns
=
{
"use"
:
"^ *use +(
\
w+) *
\
. *(
\
w+) *
\
. *
\
w+ *;"
,
"entity"
:
"^ *entity +(
\
w+) +is +(port|generic)"
,
"entity"
:
"^ *entity +(
\
w+) +is +(port|generic
|end
)"
,
"package"
:
"^ *package +(
\
w+) +is"
,
"arch_begin"
:
"^ *architecture +(
\
w+) +of +(
\
w+) +is +"
,
"arch_end"
:
"^ *end +(
\
w+) +;"
,
"instance"
:
"^ *(
\
w+) *
\
: *(
\
w+) *(port
|generic) *map
"
,
"instance_from_work_library"
:
"^ *(
\
w+) *
\
: *entity *work *
\
. *(
\
w+) *(port
|generic) *map
"
"instance"
:
"^ *(
\
w+) *
\
: *(
\
w+) *(port
*map|generic *map| *;)
"
,
"instance_from_work_library"
:
"^ *(
\
w+) *
\
: *entity *work *
\
. *(
\
w+) *(port
*map|generic *map| *;)
"
}
compiled_patterns
=
map
(
lambda
p
:
(
p
,
re
.
compile
(
patterns
[
p
])),
patterns
)
within_architecture
=
False
for
l
in
lines
:
...
...
@@ -128,7 +127,6 @@ class VHDLParser(DepParser):
continue
what
,
g
=
matches
[
0
]
if
(
what
==
"use"
):
logging
.
debug
(
"use package
%
s"
%
g
.
group
(
1
)
+
"."
+
g
.
group
(
2
)
)
dep_file
.
add_relation
(
DepRelation
(
g
.
group
(
1
)
+
"."
+
g
.
group
(
2
),
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
...
...
@@ -155,8 +153,6 @@ class VHDLParser(DepParser):
within_architecture
=
False
elif
(
what
in
[
"instance"
,
"instance_from_work_library"
]
and
within_architecture
):
logging
.
debug
(
"-> instantiates
%
s as
%
s"
%
(
g
.
group
(
1
),
g
.
group
(
2
))
)
if
(
what
==
"instance_from_work_library"
)
:
logging
.
info
(
"Mam cie !!!!!!!!!!!!!!!!!!!!
%
s"
%
g
.
group
(
2
)
)
dep_file
.
add_relation
(
DepRelation
(
g
.
group
(
2
),
DepRelation
.
USE
,
DepRelation
.
ENTITY
))
...
...
tests/questa_uvm_sv/rtl/RTLTopModuleSV.sv
View file @
d82dc290
...
...
@@ -14,7 +14,7 @@ module RTLTopModuleSV;
initial
l1a
<=
RTL_SVPackage
::
CONST
;
includeModule
incl
()
;
includeModule
SV
incl
()
;
ipcore
ip
()
;
endmodule
// RTLTopModuleSV
tests/questa_uvm_sv/rtl/RTLTopModuleVHDL.vhdl
View file @
d82dc290
...
...
@@ -23,26 +23,21 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
entity
RTLTopModuleVHDL
is
port
();
end
entity
RTLTopModuleVHDL
;
architecture
Behavioral
of
RTLTopModuleVHDL
is
component
includeModuleVHDL
is
port
();
end
component
;
signal
probe
:
STD_LOGIC
;
begin
-- architectureecture Behavioral
probe
<=
'1'
;
include_module
:
includeModuleVHDL
port
map
();
include_module
:
includeModuleVHDL
;
a
:
entity
work
.
includeModuleAVHDL
port
map
();
a
:
entity
work
.
includeModuleAVHDL
;
GEN
:
for
i
in
0
to
3
generate
B
:
entity
work
.
includeModuleBVHDL
port
map
();
B
:
entity
work
.
includeModuleBVHDL
;
end
generate
;
end
architecture
Behavioral
;
tests/questa_uvm_sv/rtl/include/includeModuleAVHDL.vhdl
View file @
d82dc290
...
...
@@ -23,7 +23,6 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
entity
includeModuleAVHDL
is
port
();
end
entity
includeModuleAVHDL
;
architecture
Behavioral
of
includeModuleAVHDL
is
...
...
tests/questa_uvm_sv/rtl/include/includeModuleBVHDL.vhdl
View file @
d82dc290
...
...
@@ -23,7 +23,6 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
entity
includeModuleBVHDL
is
port
();
end
entity
includeModuleBVHDL
;
architecture
Behavioral
of
includeModuleBVHDL
is
...
...
tests/questa_uvm_sv/rtl/include/includeModuleVHDL.vhdl
View file @
d82dc290
...
...
@@ -23,7 +23,6 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
entity
includeModuleVHDL
is
port
();
end
entity
includeModuleVHDL
;
architecture
Behavioral
of
includeModuleVHDL
is
...
...
tests/questa_uvm_sv/sim/tests/Makefile
View file @
d82dc290
...
...
@@ -115,7 +115,8 @@ work/includeModuleBVHDL/.includeModuleBVHDL_vhdl: ../../rtl/include/includeModul
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl
:
../../rtl/RTLTopModuleVHDL.vhdl
\
work/includeModuleVHDL/.includeModuleVHDL_vhdl
\
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl
\
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
...
...
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