Commit d30b4a5c authored by Benny Simonsen's avatar Benny Simonsen

Documentation updated for feature specify top_module/sim_top/syn_top library

parent b55e0560
......@@ -501,6 +501,9 @@ The following common top specific Manifest variables describes the simulation:
- ``action``: indicates that we are going to perform a simulation.
- ``sim_tool``: indicates that modelsim is going to be the simulation we are going to use.
- ``sim_top``: indicates the name of the top HDL entity/instance that is going to be simulated.
- If ``sim_top`` has no ``.``: Then sim_top is ``work.<sim_top>``
- If ``sim_top`` starts with ``.``, then sim_top is ``library.sim_top``
- If ``sim_top`` has a ``.``: ``<library name>.<sim_top entity>``, then ``sim_top`` is ``<library name>.<sim_top entity>``
- ``sim_post_cmd``: indicates a command that must be issued after the simulation process has finnished.
Now, if we want to launch the simulation, we must follow the next steps. First, get into the folder containing the top Manifest.py we want to execute and run ``hdlmake`` without arguments. e.g. for VHDL:
......@@ -669,6 +672,9 @@ We can see that the only difference is that each of the top synthesis Manifest.p
- ``syn_grade``: indicates the specific FPGA speed grade
- ``syn_package``: indicates the specific FPGA package
- ``syn_top``: indicates the name of the top HDL instance/module to be synthesized.
- If ``syn_top`` has no ``.``: Then syn_top is ``work.<syn_top>``
- If ``syn_top`` starts with ``.``, then syn_top is ``library.syn_top``
- If ``syn_top`` has a ``.``: ``<library name>.<syn_top entity>``, then ``syn_top`` is ``<library name>.<syn_top entity>``
- ``syn_project``: indicates the name of the FPGA project that is going to be created.
- ``syn_tool``: indicates the specific synthesis tool that is going to be used.
......@@ -1489,7 +1495,7 @@ Basic simulation variables:
+----------------+--------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+================+==============+=================================================================+===========+
| sim_top | str | Top level module for simulation | None |
| sim_top | str | Top level module for simulation (see note) | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| sim_tool | str | Simulation tool to be used (e.g. isim, vsim, iverilog) | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
......@@ -1498,6 +1504,13 @@ Basic simulation variables:
| sim_post_cmd | str | Command to be executed after simulation | None |
+----------------+--------------+-----------------------------------------------------------------+-----------+
Notes:
- ``sim_top``:
- If ``sim_top`` has no ``.``: Then sim_top is ``work.<sim_top>``
- If ``sim_top`` starts with ``.``, then sim_top is ``library.sim_top``
- If ``sim_top`` has a ``.``: ``<library name>.<sim_top entity>``, then ``sim_top`` is ``<library name>.<sim_top entity>``
Modelsim/VSim specific variables:
......@@ -1544,7 +1557,7 @@ Basic synthesis variables:
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+==========================+=============+=================================================================+===========+
| syn_top | str | Top level module for synthesis | None |
| syn_top | str | Top level module for synthesis (see note) | None |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
| syn_tool | str | Tool to be used in the synthesis | None |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
......@@ -1579,6 +1592,13 @@ Basic synthesis variables:
| syn_post_bitstream_cmd | str | Command to be executed after synthesis: bitstream | '' |
+--------------------------+-------------+-----------------------------------------------------------------+-----------+
Notes:
- ``syn_top``:
- If ``syn_top`` has no ``.``: Then syn_top is ``work.<syn_top>``
- If ``syn_top`` starts with ``.``, then syn_top is ``library.syn_top``
- If ``syn_top`` has a ``.``: ``<library name>.<syn_top entity>``, then ``syn_top`` is ``<library name>.<syn_top entity>``
Altera Quartus II / Prime specific variables:
......
......@@ -39,7 +39,7 @@ class ManifestParser(ConfigParser):
general_options = [
{'name': 'top_module',
'default': None,
'help': "Top level HDL entity for synthesis and simulation",
'help': "Top level HDL entity for synthesis and simulation, if starts with dot, then library=value of library, else lib_name.entity_name or if no dot then library is work",
'type': ''},
{'name': 'extra_modules',
'default': None,
......@@ -130,7 +130,7 @@ class ManifestParser(ConfigParser):
'type': ''},
{'name': 'syn_top',
'default': None,
'help': "Top level module for synthesis",
'help': "Top level module for synthesis. Optionally prefixed with library, see top_module",
'type': ''},
{'name': 'syn_project',
'default': None,
......@@ -212,7 +212,7 @@ class ManifestParser(ConfigParser):
sim_options = [
{'name': 'sim_top',
'default': None,
'help': "Top level module for simulation",
'help': "Top level module for simulation. Optionally prefixed with library, see top_module",
'type': ''},
{'name': 'sim_tool',
'default': None,
......
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