Commit cc56877a authored by garcialasheras's avatar garcialasheras

Simple 8-bit counter test for syn/sim, VHDL/Verilog

parent 1d66eb8b
//-----------------------------------------------------
// Design : Simple 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//-----------------------------------------------------
module counter (
clock,
clear,
count,
Q
);
//--------- Output Ports ------------------------------
output [7:0] Q;
//--------- Input Ports -------------------------------
input clock, clear, count;
//--------- Internal Variables ------------------------
reg [7:0] Q;
//--------- Code Starts Here --------------------------
always @(posedge clock)
if (clear) begin
Q <= 8'b0 ;
end else if (count) begin
Q <= Q + 1;
end
endmodule
-------------------------------------------------------
-- Design : Simple 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
-------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------
entity counter is
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end counter;
-------------------------------------------------------
architecture behv of counter is
signal Pre_Q: unsigned(7 downto 0);
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= "00000000";
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= std_logic_vector(Pre_Q);
end behv;
-------------------------------------------------------
asim +access +r counter_tb
trace -rec *
run 6 us
endsim
quit
action = "simulation"
sim_tool = "aldec"
top_module = "counter_tb"
sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "aldec"
top_module = "counter_tb"
sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
action = "simulation"
sim_tool = "ghdl"
top_module = "counter_tb"
sim_post_cmd = "ghdl -r counter_tb --stop-time=6us --vcd=counter_tb.vcd; gtkwave counter_tb.vcd"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
wave add /
vcd dumpfile counter_tb.vcd
vcd dumpvars -m counter_tb -l 1
run 6000 ns
#exit
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "counter_tb"
sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "counter_tb"
sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
action = "simulation"
sim_tool = "iverilog"
top_module = "counter_tb"
sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
vcd file counter_tb.vcd;
vcd add -r /*;
add wave *
run 6000ns;
view wave;
target = "lattice"
action = "synthesis"
syn_device = "lfxp2-5e"
syn_grade = "-6"
syn_package = "tn144c"
syn_top = "brevia2_top"
syn_project = "demo"
syn_tool = "diamond"
modules = {
"local" : [ "../../../top/brevia2_dk/verilog" ],
}
target = "lattice"
action = "synthesis"
syn_device = "lfxp2-5e"
syn_grade = "-6"
syn_package = "tn144c"
syn_top = "brevia2_top"
syn_project = "demo"
syn_tool = "diamond"
modules = {
"local" : [ "../../../top/brevia2_dk/vhdl" ],
}
target = "altera"
action = "synthesis"
syn_device = "ep3c25"
syn_grade = "c6"
syn_package = "f324"
syn_top = "cyclone3_top"
syn_project = "demo"
syn_tool = "quartus"
quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule = "../../../top/cyclone3_sk/module.tcl"
modules = {
"local" : [ "../../../top/cyclone3_sk/verilog" ],
}
target = "altera"
action = "synthesis"
syn_device = "ep3c25"
syn_grade = "c6"
syn_package = "f324"
syn_top = "cyclone3_top"
syn_project = "demo"
syn_tool = "quartus"
quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule = "../../../top/cyclone3_sk/module.tcl"
modules = {
"local" : [ "../../../top/cyclone3_sk/vhdl" ],
}
target = "microsemi"
action = "synthesis"
syn_device = "a3p250"
syn_grade = "-2"
syn_package = "208 pqfp"
syn_top = "proasic3_top"
syn_project = "demo"
syn_tool = "libero"
modules = {
"local" : [ "../../../top/proasic3_sk/verilog" ],
}
target = "microsemi"
action = "synthesis"
syn_device = "a3p250"
syn_grade = "-2"
syn_package = "208 pqfp"
syn_top = "proasic3_top"
syn_project = "demo"
syn_tool = "libero"
modules = {
"local" : [ "../../../top/proasic3_sk/vhdl" ],
}
......@@ -4,12 +4,11 @@ action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "half2"
syn_project = "half2.xise"
syn_top = "spec_top"
syn_project = "demo.xise"
syn_tool = "ise"
files = [
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
modules = {
"local" : [ "../../../top/spec_v4/verilog" ],
}
......@@ -4,9 +4,11 @@ action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "myfilter"
syn_project = "myfilter.xise"
syn_top = "spec_top"
syn_project = "demo.xise"
syn_tool = "ise"
files = ["../../../modules/fir/myfilter.vhd"]
modules = {
"local" : [ "../../../top/spec_v4/vhdl" ],
}
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "demo"
syn_tool = "planahead"
modules = {
"local" : [ "../../../top/spec_v4/verilog" ],
}
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "demo"
syn_tool = "planahead"
modules = {
"local" : [ "../../../top/spec_v4/vhdl" ],
}
files = [
"counter_tb.v",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------
// Design : Simple testbench for an 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module counter_tb();
// Declare inputs as regs and outputs as wires
reg clock, clear, count;
wire [7:0] Q;
// Initialize all variables
initial begin
$dumpfile("counter_tb.vcd");
$dumpvars(0,counter_tb);
$display ("time\t clock clear count Q");
$monitor ("%g\t %b %b %b %b",
$time, clock, clear, count, Q);
clock = 1; // initial value of clock
clear = 0; // initial value of clear
count = 0; // initial value of count enable
#5 clear = 1; // Assert the clear signal
#10 clear = 0; // De-assert clear signal
#10 count = 1; // Start count
#2000 count = 0; // De-assert count enable
#5 $finish; // Terminate simulation
end
// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
counter U_counter (
clock,
clear,
count,
Q
);
endmodule
files = [
"counter_tb.vhd",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
----------------------------------------------------------
-- Design : Simple testbench for an 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity counter_tb is -- entity declaration
end counter_tb;
-----------------------------------------------------------------------
architecture testbench of counter_tb is
component counter
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal t_clock: std_logic;
signal t_clear: std_logic;
signal t_count: std_logic;
signal t_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter port map (t_clock, t_clear, t_count, t_Q);
process
begin
t_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
t_clock <= '1';
wait for 5 ns;
end process;
process
begin
t_clear <= '1'; -- start counting
t_count <= '1';
wait for 50 ns;
t_clear <= '0'; -- clear output
wait for 1000 ns;
report "Testbench of Adder completed successfully!"
severity note;
wait;
end process;
end testbench;
----------------------------------------------------------------
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "led_o_0" SITE "46" ;
LOCATE COMP "led_o_1" SITE "45" ;
LOCATE COMP "led_o_2" SITE "44" ;
LOCATE COMP "led_o_3" SITE "43" ;
LOCATE COMP "led_o_4" SITE "40" ;
LOCATE COMP "led_o_5" SITE "39" ;
LOCATE COMP "led_o_6" SITE "38" ;
LOCATE COMP "led_o_7" SITE "37" ;
LOCATE COMP "clear_i" SITE "50" ;
LOCATE COMP "count_i" SITE "53" ;
LOCATE COMP "clock_i" SITE "21" ;
LOCATE COMP "clken_o" SITE "22" ;
files = [
"brevia2_top.v",
"../brevia2_top.lpf",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------
// Design : Counter verilog top module, Lattice Brevia2
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module brevia2_top (
clear_i,
count_i,
clock_i,
clken_o,
led_o
);
input clear_i, count_i, clock_i;
output clken_o;
output [7:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign clken_o = 1;
assign s_clear = ~clear_i;
assign s_count = ~count_i;
assign led_o[7:0] = ~s_Q[7:0];
endmodule
files = [
"brevia2_top.vhd",
"../brevia2_top.lpf",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
----------------------------------------------------------
-- Design : Counter VHDL top module, Lattice Brevia2
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity brevia2_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
clken_o: out std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end brevia2_top;
----------------------------------------------------------
architecture structure of brevia2_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
clken_o <= '1';
s_clear <= not clear_i;
s_count <= not count_i;
led_o <= not s_Q;
end architecture structure;
----------------------------------------------------------------
set module [lindex $quartus(args) 0]
if [string match "quartus_map" $module] {
# Include commands here that are run
# after analysis and synthesis
post_message "Running after analysis & synthesis"
}
if [string match "quartus_fit" $module] {
# Include commands here that are run
# after fitter (Place & Route)
post_message "Running after place & route"
}
if [string match "quartus_asm" $module] {
# Include commands here that are run
# after assembler (Generate programming files)
post_message "Running after timing analysis"
}
if [string match "quartus_tan" $module] {
# Include commands here that are run
# after timing analysis
post_message "Running after timing analysis"
}
post_message "Assigning pinout"
# Load Quartus II Tcl Project package
package require ::quartus::project
project_open -revision demo demo
set_location_assignment PIN_F1 -to clear_i
set_location_assignment PIN_F2 -to count_i
set_location_assignment PIN_B9 -to clock_i
set_location_assignment PIN_N9 -to led_o[3]
set_location_assignment PIN_N12 -to led_o[2]
set_location_assignment PIN_P12 -to led_o[1]
set_location_assignment PIN_P13 -to led_o[0]
# Commit assignments
export_assignments
project_close
files = [
"cyclone3_top.v",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------------------
// Design : Counter verilog top module, Altera CycloneIII Starter Kit
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------------------
module cyclone3_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [3:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = ~clear_i;
assign s_count = ~count_i;
assign led_o[3:0] = ~s_Q[7:4];
endmodule
files = [
"cyclone3_top.vhd",
]
modules = {
"local" : [ ],
}
----------------------------------------------------------------------
-- Design : Counter VHDL top module, Altera CycloneIII Starter Kit
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cyclone3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end cyclone3_top;
----------------------------------------------------------------------
architecture structure of cyclone3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
# Microsemi Physical design constraints file
# Family: ProASIC3 , Die: A3P250 , Package: 208 PQFP , Speed grade: -2
#
# IO banks setting
#
set_iobank Bank3 -vcci 3.30 -fixed no
set_iobank Bank2 -vcci 3.30 -fixed no
set_iobank Bank1 -vcci 3.30 -fixed no
set_iobank Bank0 -vcci 3.30 -fixed no
#
# I/O constraints
#
set_io led_o\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 63 -fixed yes
set_io led_o\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 61 -fixed yes
set_io led_o\[2\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 60 -fixed yes
set_io led_o\[3\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 59 -fixed yes
set_io led_o\[4\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 58 -fixed yes
set_io led_o\[5\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 57 -fixed yes
set_io led_o\[6\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 56 -fixed yes
set_io led_o\[7\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 55 -fixed yes
set_io clear_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 68 -fixed yes
set_io count_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 67 -fixed yes
# 40MHz clock
set_io clock_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 26 -fixed yes
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top
# Other Constraints
files = [
"proasic3_top.v",
"../proasic3_top.pdc",
"../proasic3_top.sdc",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//---------------------------------------------------------------------
// Design : Counter verilog top module, Microsemi ProASIC3 Starter Kit
// Author : Javier D. Garcia-Lasheras
//---------------------------------------------------------------------
module proasic3_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [7:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = clear_i;
assign s_count = count_i;
assign led_o[7:0] = s_Q[7:0];
endmodule
files = [
"proasic3_top.vhd",
"../proasic3_top.pdc",
"../proasic3_top.sdc",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, Microsemi ProASIC3 Starter Kit
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity proasic3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end proasic3_top;
-----------------------------------------------------------------------
architecture structure of proasic3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= clear_i;
s_count <= count_i;
led_o <= s_Q;
end architecture structure;
----------------------------------------------------------------
NET "CLOCK_I" LOC = H12;
NET "CLOCK_I" IOSTANDARD = "LVCMOS18";
NET "COUNT_I" LOC = C22;
NET "COUNT_I" IOSTANDARD = "LVCMOS18";
NET "CLEAR_I" LOC = D21;
NET "CLEAR_I" IOSTANDARD = "LVCMOS18";
NET "LED_O[0]" LOC = G19;
NET "LED_O[0]" IOSTANDARD = "LVCMOS18";
NET "LED_O[1]" LOC = F20;
NET "LED_O[1]" IOSTANDARD = "LVCMOS18";
NET "LED_O[2]" LOC = F18;
NET "LED_O[2]" IOSTANDARD = "LVCMOS18";
NET "LED_O[3]" LOC = C20;
NET "LED_O[3]" IOSTANDARD = "LVCMOS18";
files = [ "spec_top.v", "../spec_top.ucf" ]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//---------------------------------------------------------------------
// Design : Counter verilog top module, SPEC (Simple PCIe Carrier)
// Author : Javier D. Garcia-Lasheras
//---------------------------------------------------------------------
module spec_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [3:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = ~clear_i;
assign s_count = ~count_i;
assign led_o[3:0] = ~s_Q[7:4];
endmodule
files = [ "spec_top.vhd", "../spec_top.ucf" ]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier)
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end spec_top;
-----------------------------------------------------------------------
architecture structure of spec_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
// Combined half-band filter and decimator
// See concept1.eps for general DSP idea
// See actual2.eps for graphical DSP representation
// Half-band filter configuration is
// -1 + 9 z^{-2} + 16 z^{-3} + 9 z^{-4} - 1 z^{-6}
// Decimation is controlled by the ab input, which _must_
// be clk/2. Output d gives a results when ab is low, and
// b results when ab is high. b results are delayed one
// cycle, corresponding to something like simultaneous
// sampling at the input.
// See actual2.eps
// Total 5 cycle latency for a, 6 cycles for b.
// Uses about 172 Slice Flip Flops and 174 4LUTs in Spartan-3.
// Larry Doolittle, LBNL, Oct. 2012
`timescale 1ns / 1ns
module half2(
input clk, // timespec 5.2 ns
input signed [15:0] a,
input signed [15:0] b,
input ab,
output signed [16:0] d
);
// buffer B one cycle, provides "simultaneous sampling"
reg [15:0] bb=0; always @(posedge clk) bb <= b;
// input switch
// left and right take their names from actual2.eps
wire signed [15:0] left = ab ? a : bb;
wire signed [15:0] right = ab ? bb : a;
wire signed [15:0] dl1;
reg_delay #(.dw(16), .len(3)) l1(.clk(clk),.gate(1'b1),.din(left),.dout(dl1));
wire signed [15:0] dr1, dr2;
reg_delay #(.dw(16), .len(2)) r1(.clk(clk),.gate(1'b1),.din(right),.dout(dr1));
reg_delay #(.dw(16), .len(4)) r2(.clk(clk),.gate(1'b1),.din(dr1), .dout(dr2));
`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x : {x[old],{new{~x[old]}}})
reg signed [16:0] s1=0, s2=0;
reg signed [20:0] m9=0;
reg signed [21:0] s3=0, s4=0;
always @(posedge clk) begin
s1 <= right + dr1;
s2 <= right + dr2;
m9 <= s1 + (s1<<<3);
s3 <= m9 + (dl1<<<4) + 8; // un-bias the truncation step
s4 <= s3 - s2;
end
wire signed [17:0] penult = s4[21:4]; // truncate 4 lsb
assign d = `SAT(penult,17,16); // clip 1 msb
endmodule
`timescale 1ns / 1ns
// sine-based testing of pass band on channel b is quite stringent:
// reference sine wave has no phase shift (execpt for compensation of
// the pipeline delay), and a small amplitude change (predicatble from
// theory for the non-DC input). Only +/-1 bit error is allowed, with
// almost no bias. rms error should in principle be 1/sqrt(12) = 0.29,
// we demand it be less than 0.33.
module half2_tb;
reg clk;
reg tracea=0,traceb=0;
reg peak_fail=0, avg_fail=0, rms_fail=0, fail=0;
integer cc, nsamp=0, offbyone=0, sum=0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("half2.vcd");
$dumpvars(5,half2_tb);
end
if ($test$plusargs("tracea")) tracea=1;
if ($test$plusargs("traceb")) traceb=1;
for (cc=0; cc<140; cc=cc+1) begin
clk=0; #5;
clk=1; #5;
end
rms_fail = offbyone > (nsamp+2)/3;
avg_fail = (sum > 4) || (sum < -4);
fail = peak_fail | avg_fail | rms_fail;
$display("x %d %d %d %d %s",nsamp,offbyone,sum,peak_fail,fail?"FAIL":"PASS");
$finish();
end
reg signed [15:0] ina=0, inb=0, sine=0;
reg signed [16:0] sineref=0;
reg ing=0;
integer noise;
integer nseed=1234;
reg ab=0;
always @(posedge clk) begin
ab <= ~ab;
sine = $floor(30000.0*$sin((cc )*0.1596)+0.5);
sineref = $floor(59992.8*$sin((cc-6)*0.1596)+0.5);
ina <= (cc==4 || cc==17) ? 1024 : 0;
//inb <= (cc>30) ? 28000 : -28000;
inb <= sine;
end
wire signed [16:0] outd;
half2 dut(.clk(clk), .a(ina), .b(inb), .ab(ab), .d(outd));
reg fault;
always @(negedge clk) begin
fault=0;
if (ab && cc>10) begin
nsamp = nsamp+1;
sum = sum + outd - sineref;
if (outd!=sineref) offbyone=offbyone+1;
fault = (outd>sineref+1) || (outd<sineref-1);
if (fault) peak_fail=1;
end
if ((tracea && (ab==0)) || (traceb && (ab==1)))
$display("%d %d %d %d %d %d", ab, ina, inb, outd, sineref, fault);
end
endmodule
// Combined half-band filter and decimator
// See concept1.eps for general DSP idea
// See actual3.eps for graphical DSP representation
// Half-band filter configuration is
// -1 + 9 z^{-2} + 16 z^{-3} + 9 z^{-4} - 1 z^{-6}
// This version set up for input streams that are already
// two-channel interleaved..
// Decimation is controlled by the ab input, which _must_
// be clk/4. Output d gives a results when ab is low, and
// b results when ab is high. b results are delayed one
// cycle, corresponding to something like simultaneous
// sampling at the input.
// Total 5 cycle latency for a, 6 cycles for b.
// Uses about 172 Slice Flip Flops and 174 4LUTs in Spartan-3.
// Larry Doolittle, LBNL, Oct. 2012
`timescale 1ns / 1ns
module half3(
input clk, // timespec 5.2 ns
input signed [15:0] a,
input signed [15:0] b,
input ab,
output signed [16:0] d
);
// buffer B two cycles, provides "simultaneous sampling"
reg [15:0] b1=0; always @(posedge clk) b1 <= b;
reg [15:0] bb=0; always @(posedge clk) bb <= b1;
// input switch
// left and right take their names from actual3.eps
wire signed [15:0] left = ab ? a : bb;
wire signed [15:0] right = ab ? bb : a;
wire signed [15:0] dl1;
reg_delay #(.dw(16), .len(6)) l1(.clk(clk),.gate(1'b1),.din(left),.dout(dl1));
wire signed [15:0] dr1, dr2;
reg_delay #(.dw(16), .len(4)) r1(.clk(clk),.gate(1'b1),.din(right),.dout(dr1));
reg_delay #(.dw(16), .len(8)) r2(.clk(clk),.gate(1'b1),.din(dr1), .dout(dr2));
`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x : {x[old],{new{~x[old]}}})
reg signed [16:0] s1=0, s2=0;
reg signed [20:0] m9=0, m9d=0, m9dd=0;
reg signed [21:0] s3=0, s4=0;
always @(posedge clk) begin
s1 <= right + dr1;
s2 <= right + dr2;
m9 <= s1 + (s1<<<3);
m9d <= m9;
m9dd <= m9d;
s3 <= m9dd + (dl1<<<4) + 8; // un-bias the truncation step
s4 <= s3 - s2;
end
wire signed [17:0] penult = s4[21:4]; // truncate 4 lsb
assign d = `SAT(penult,17,16); // clip 1 msb
endmodule
`timescale 1ns / 1ns
// sine-based testing of pass band on channel b is quite stringent:
// reference sine wave has no phase shift (execpt for compensation of
// the pipeline delay), and a small amplitude change (predicatble from
// theory for the non-DC input). Only +/-1 bit error is allowed, with
// almost no bias. rms error should in principle be 1/sqrt(12) = 0.29,
// we demand it be less than 0.33.
module half3_tb;
reg clk;
reg tracex=0,tracea=0,traceb=0;
reg peak_fail=0, avg_fail=0, rms_fail=0, fail=0;
integer cc, nsamp=0, offbyone=0, sum=0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("half3.vcd");
$dumpvars(5,half3_tb);
end
if ($test$plusargs("tracex")) tracex=1;
if ($test$plusargs("tracea")) tracea=1;
if ($test$plusargs("traceb")) traceb=1;
for (cc=0; cc<140; cc=cc+1) begin
clk=0; #5;
clk=1; #5;
end
rms_fail = offbyone > (nsamp+2)/3;
avg_fail = (sum > 4) || (sum < -4);
fail = peak_fail | avg_fail | rms_fail;
$display("x %d %d %d %d %s",nsamp,offbyone,sum,peak_fail,fail?"FAIL":"PASS");
$finish();
end
reg signed [15:0] ina=0, inb=0, sine=0;
reg signed [16:0] sineref=0;
reg ing=0;
integer noise;
integer nseed=1234;
reg [1:0] abc=0;
wire ab=abc[1];
wire cs=abc[0]; // cos vs. sin on a and b inputs
always @(posedge clk) begin
abc <= abc+1;
sine = $floor(30000.0*$sin((cc )*0.0798)+0.5);
sineref = $floor(59992.8*$sin((cc-10)*0.0798)+0.5);
ina <= (cc==4 || cc==17 || cc==30 || cc==43) ? 1024 : 0;
//inb <= (cc>30) ? 28000 : -28000;
inb <= cs ? sine : 0;
end
wire signed [16:0] outd;
half3 dut(.clk(clk), .a(ina), .b(inb), .ab(ab), .d(outd));
reg fault;
always @(negedge clk) begin
fault=0;
if ((abc==0) && (cc>16)) begin
nsamp = nsamp+1;
sum = sum + outd - sineref;
if (outd!=sineref) offbyone=offbyone+1;
fault = (outd>sineref+1) || (outd<sineref-1);
if (fault) peak_fail=1;
end
if (tracex | (tracea & (ab==0)) | (traceb & (abc==0)))
$display("%d %d %d %d %d %d", abc, ina, inb, outd, sineref, outd-sineref);
end
endmodule
`timescale 1ns / 1ns
module reg_delay(clk, gate, din, dout);
parameter dw=16;
parameter len=4;
input clk;
input gate;
input [dw-1:0] din;
output [dw-1:0] dout;
// len clocks of delay. Xilinx should turn this into
// dw*floor((len+15)/16)
// SRL16 shift registers, since there are no resets.
generate if (len > 1) begin: usual
reg [dw*len-1:0] shifter=0;
always @(posedge clk) if (gate) shifter <= {shifter[dw*len-1-dw:0],din};
assign dout = shifter[dw*len-1:dw*len-dw];
end else if (len > 0) begin: degen1
reg [dw*len-1:0] shifter=0;
always @(posedge clk) if (gate) shifter <= din;
assign dout = shifter[dw*len-1:dw*len-dw];
end else begin: degen0
assign dout = din;
end
endgenerate
endmodule
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myfilter is
port (
clk : in std_logic;
rst : in std_logic;
sig_in : in signed(15 downto 0);
sig_out : out signed(15 downto 0)
);
end entity;
architecture Direct_Form_I_Transposed of myfilter is
-- This file has been generated with Libre-FDATool
-- Creation Time: 2014-04-26 01:36
-- Z^-1 delay blocks
type zb_array is array (0 to 6) of signed(30 downto 0);
signal zb, zb_next: zb_array;
-- Filter constants
type b_array is array (0 to 7) of signed(15 downto 0);
signal b: b_array;
-- Filter Adders
type sum_b_array is array (0 to 6) of signed(30 downto 0);
signal sb: sum_b_array;
-- Filter Products
type product_b_array is array (0 to 7) of signed(30 downto 0);
signal pb: product_b_array;
type product_b_temp_array is array (0 to 7) of signed(31 downto 0);
signal pb_temp: product_b_temp_array;
-- Feedback loop accumulator
signal v: signed(15 downto 0);
-- Begin Architecture
begin
-- Assign Coefficients
b(0) <= "0000111000100010"; -- 0.110401
b(1) <= "0000111110110011"; -- 0.122661
b(2) <= "0001000011001101"; -- 0.131255
b(3) <= "0001000101011110"; -- 0.135682
b(4) <= "0001000101011110"; -- 0.135682
b(5) <= "0001000011001101"; -- 0.131255
b(6) <= "0000111110110011"; -- 0.122661
b(7) <= "0000111000100010"; -- 0.110401
----------------------------------
-- Sequential logic description --
----------------------------------
-- Sequential delay chain for the B block
seq_b_block: for x in 0 to 6 generate
reg_b: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
zb(x) <= (others => '0');
else
zb(x) <= zb_next(x);
end if;
end if;
end process reg_b;
end generate seq_b_block;
----------------------------------
-- Processing logic description --
----------------------------------
-- Bypassing the A processing block
v <= sig_in;
-- Processing block for the Filter structure B side
process_b_block: for n in 0 to 7 generate
-- Calculate products being generated
pb_temp(n) <= v * b(n);
pb(n) <= pb_temp(n)(30 downto 0);
-- Calculate sums being generated
add_b_block: if (n < 7) generate
sb(n) <= pb(n) + zb(n);
end generate add_b_block;
-- Calculate values for zb_next
-- ... those halfway in the loop
mid_b_tap: if (n < 6) generate
zb_next(n) <= sb(n+1);
end generate mid_b_tap;
-- ... final structure
final_b_tap: if (n = 6) generate
zb_next(n) <= pb(n+1);
end generate final_b_tap;
end generate process_b_block;
-- Convert Fixed Point to sig_out from sb(0)
sig_out(15 downto 15) <= sb(0)(30 downto 30);
sig_out(14 downto 0) <= sb(0)(29 downto 15);
end Direct_Form_I_Transposed;
This diff is collapsed.
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "half2_tb"
files = [
"../../../modules/filtdec/half2_tb.v",
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
vcd dumpfile half2_tb.vcd
vcd dumpvars -m half2_tb -l 1
run 100000 ns
exit
#!/bin/bash
hdlmake
make && make fuse TOP_MODULE=half2_tb && ./isim_proj -tclbatch isim_cmd
action = "simulation"
target = "altera"
sim_tool = "modelsim"
top_module = "half2_tb"
files = [
"../../../modules/filtdec/half2_tb.v",
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
#!/bin/bash
hdlmake
make
vsim -c -do vsim.do half2_tb
vcd file half2_tb.vcd;
vcd add -r /*;
run 100000ns;
quit;
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "tb_myfilter"
files = [
"../../../modules/fir/tb_myfilter.vhd",
"../../../modules/fir/myfilter.vhd"
]
vcd dumpfile tb_myfilter.vcd
vcd dumpvars -m tb_myfilter -l 1
run 100000 ns
exit
#!/bin/bash
hdlmake
make && make fuse TOP_MODULE=tb_myfilter && ./isim_proj -tclbatch isim_cmd
action = "simulation"
target = "altera"
sim_tool = "modelsim"
top_module = "tb_myfilter"
files = [
"../../../modules/fir/tb_myfilter.vhd",
"../../../modules/fir/myfilter.vhd"
]
#!/bin/bash
hdlmake
make
vsim -c -do vsim.do tb_myfilter
vcd file myfilter.vcd;
vcd add -r /*;
run 100000ns;
quit;
target = "altera"
action = "synthesis"
# Supported families on tools/quartus.py
# Quartus Web only supports the family ep2agx45:
syn_device = "ep2agx45cu"
syn_grade = "c6"
syn_package = "17"
syn_top = "half2"
syn_project = "half2"
#syn_tool = "quartus"
files = [
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
#!/bin/bash
hdlmake quartus-project
# Quartus bin needs to be exported to path
quartus_sh --tcl_eval load_package flow \; project_open half2 \; execute_flow -compile
#!/bin/bash
echo "set the appropriated HDLMAKE_RSYNTH variables in this file"
export HDLMAKE_RSYNTH_USER=javi
export HDLMAKE_RSYNTH_ISE_PATH="/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/"
export HDLMAKE_RSYNTH_SERVER="192.168.0.17"
hdlmake
make remote
make sync
make cleanremote
target = "altera"
action = "synthesis"
# Supported families on tools/quartus.py
# Quartus Web only supports the family ep2agx45:
syn_device = "ep2agx45cu"
syn_grade = "c6"
syn_package = "17"
syn_top = "myfilter"
syn_project = "myfilter"
#syn_tool = "quartus"
files = ["../../../modules/fir/myfilter.vhd"]
#!/bin/bash
hdlmake quartus-project
# Quartus bin needs to be exported to path
quartus_sh --tcl_eval load_package flow \; project_open myfilter \; execute_flow -compile
#!/bin/bash
echo "set the appropriated HDLMAKE_RSYNTH variables in this file"
export HDLMAKE_RSYNTH_USER=javi
export HDLMAKE_RSYNTH_ISE_PATH="/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/"
export HDLMAKE_RSYNTH_SERVER="192.168.0.17"
hdlmake
make remote
make sync
make cleanremote
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "top_module"
files = [ "top_module_tb.vhd", "top_module.vhd" ]
#!/bin/bash
# Tests for empty parameter
if [ -z $1 ] ; then
echo "You must specify a top module testbench!";
echo "Usage: $0 <TOP_MODULE_WITHOUT_EXTENSION>";
exit 1;
fi
make && make fuse TOP_MODULE=$1 && ./isim_proj -view wave.wcfg -tclbatch isim_cmd -gui
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity top_module is
generic(
g_clk_period : natural := 100000000;
g_sim : boolean := true
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
function f_ceil_log2(x : natural) return natural is
begin
if x <= 1 then
return 0;
else
return f_ceil_log2((x+1)/2) + 1;
end if;
end f_ceil_log2;
-- Constant declaration
constant c_blink_num_pins : natural := 8;
constant c_counter_width : natural := f_ceil_log2(c_blink_num_pins);
constant c_counter_full : natural := c_blink_num_pins;
constant c_sim_clk_period : natural := 1;
constant c_clk_period : natural := g_clk_period;
-- Global clock
signal clk_sys : std_logic;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
signal s_counter_full : unsigned(c_counter_width-1 downto 0);
signal s_blink : std_logic_vector(c_blink_num_pins-1 downto 0);
signal rst_n : std_logic;
begin
clk_sys <= clk_i;
rst_n <= rst_n_i;
gen_sim_clk_period : if g_sim = true generate
s_counter_full <= to_unsigned(c_sim_clk_period, c_counter_width);
end generate;
gen_syn_clk_period : if g_sim = false generate
s_counter_full <= to_unsigned(c_clk_period, c_counter_width);
end generate;
p_counter : process (clk_sys)
begin
if rising_edge(clk_sys) then
if rst_n = '0' then
s_counter <= (others => '0');
s_blink <= x"01";
else
if (s_counter = s_counter_full-1) then
s_counter <= (others => '0');
s_blink <= s_blink(c_blink_num_pins-2 downto 0) & s_blink(c_blink_num_pins-1);
else
s_counter <= s_counter + 1;
end if;
end if;
end if;
end process;
blink_o <= s_blink;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_module_tb is -- entity declaration
end top_module_tb;
architecture sim of top_module_tb is
-- 100.00 MHz clock
constant c_clk_period : time := 10.00 ns;
constant c_rst_cycles : natural := 4;
constant c_sim_time : time := 1000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
signal clk100 : std_logic := '0';
signal s_locked : std_logic;
signal s_blink : std_logic_vector(7 downto 0);
signal s_rst_n : std_logic;
-- Components
component top_module
generic(
g_clk_period : natural := 100000000;
g_sim : boolean := true
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end component;
-- Functions
--function calculate_next_input_sample(sample_number : in integer) return std_logic_vector is
-- variable A : real := 1.0; -- Amplitude for wave
-- variable F : real := 100.0; -- Frequency for wave
-- variable P : real := 0.0; -- Phase for wave
-- variable theta : real;
-- variable y : real; -- The calculated value as a real
-- variable y_int : integer; -- The calculated value as an integer
-- variable result : std_logic_vector(c_ip_width-1 downto 0);
-- variable number_of_samples : real := 100.0 * real(47);
--begin
-- theta := (2.0 * MATH_PI * F * real(sample_number mod integer(number_of_samples))) / number_of_samples;
-- y := A * sin(theta + P);
-- y_int := integer(round(y * real(2**(c_ip_width-2))));
-- result := std_logic_vector(to_signed(y_int, c_ip_width));
-- return result;
--end function calculate_next_input_sample;
begin
cmp_top_module : top_module
generic map
(
g_clk_period => 4,
g_sim => false
)
port map
(
clk_i => clk100,
rst_n_i => s_rst_n,
blink_o => s_blink
);
p_clk_gen : process is
begin
while g_end_simulation = false loop
wait for c_clk_period/2;
clk100 <= not clk100;
wait for c_clk_period/2;
clk100 <= not clk100;
end loop;
wait; -- simulation stops here
end process p_clk_gen;
p_main_simulation : process is
begin
s_rst_n <= '0';
wait for c_rst_cycles*c_clk_period;
s_rst_n <= '1';
wait for 100*c_clk_period;
-- End simualtion
g_end_simulation <= true;
end process p_main_simulation;
end sim;
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="top_module_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="15" />
<wvobject fp_name="/top_module_tb/g_end_simulation" type="other" db_ref_id="1">
<obj_property name="ElementShortName">g_end_simulation</obj_property>
<obj_property name="ObjectShortName">g_end_simulation</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/clk100" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk100</obj_property>
<obj_property name="ObjectShortName">clk100</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/s_locked" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_locked</obj_property>
<obj_property name="ObjectShortName">s_locked</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/s_blink" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_blink[7:0]</obj_property>
<obj_property name="ObjectShortName">s_blink[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/c_clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_clk_period</obj_property>
<obj_property name="ObjectShortName">c_clk_period</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/c_sim_time" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_sim_time</obj_property>
<obj_property name="ObjectShortName">c_sim_time</obj_property>
</wvobject>
<wvobject fp_name="divider20" type="divider">
<obj_property name="label">cmp_top_module</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/blink_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">blink_o[7:0]</obj_property>
<obj_property name="ObjectShortName">blink_o[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/clk_sys" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_sys</obj_property>
<obj_property name="ObjectShortName">clk_sys</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/s_counter" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_counter[2:0]</obj_property>
<obj_property name="ObjectShortName">s_counter[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/s_blink" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_blink[7:0]</obj_property>
<obj_property name="ObjectShortName">s_blink[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/c_blink_num_pins" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_blink_num_pins</obj_property>
<obj_property name="ObjectShortName">c_blink_num_pins</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/c_counter_width" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_counter_width</obj_property>
<obj_property name="ObjectShortName">c_counter_width</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/s_counter_full" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_counter_full[2:0]</obj_property>
<obj_property name="ObjectShortName">s_counter_full[2:0]</obj_property>
</wvobject>
</wave_config>
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