Commit cc56877a authored by garcialasheras's avatar garcialasheras

Simple 8-bit counter test for syn/sim, VHDL/Verilog

parent 1d66eb8b
//-----------------------------------------------------
// Design : Simple 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//-----------------------------------------------------
module counter (
clock,
clear,
count,
Q
);
//--------- Output Ports ------------------------------
output [7:0] Q;
//--------- Input Ports -------------------------------
input clock, clear, count;
//--------- Internal Variables ------------------------
reg [7:0] Q;
//--------- Code Starts Here --------------------------
always @(posedge clock)
if (clear) begin
Q <= 8'b0 ;
end else if (count) begin
Q <= Q + 1;
end
endmodule
-------------------------------------------------------
-- Design : Simple 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
-------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------
entity counter is
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end counter;
-------------------------------------------------------
architecture behv of counter is
signal Pre_Q: unsigned(7 downto 0);
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= "00000000";
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= std_logic_vector(Pre_Q);
end behv;
-------------------------------------------------------
asim +access +r counter_tb
trace -rec *
run 6 us
endsim
quit
action = "simulation"
sim_tool = "aldec"
top_module = "counter_tb"
sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "aldec"
top_module = "counter_tb"
sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
action = "simulation"
sim_tool = "ghdl"
top_module = "counter_tb"
sim_post_cmd = "ghdl -r counter_tb --stop-time=6us --vcd=counter_tb.vcd; gtkwave counter_tb.vcd"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
wave add /
vcd dumpfile counter_tb.vcd
vcd dumpvars -m counter_tb -l 1
run 6000 ns
#exit
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "counter_tb"
sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "counter_tb"
sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
action = "simulation"
sim_tool = "iverilog"
top_module = "counter_tb"
sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
vcd file counter_tb.vcd;
vcd add -r /*;
add wave *
run 6000ns;
view wave;
target = "lattice"
action = "synthesis"
syn_device = "lfxp2-5e"
syn_grade = "-6"
syn_package = "tn144c"
syn_top = "brevia2_top"
syn_project = "demo"
syn_tool = "diamond"
modules = {
"local" : [ "../../../top/brevia2_dk/verilog" ],
}
target = "lattice"
action = "synthesis"
syn_device = "lfxp2-5e"
syn_grade = "-6"
syn_package = "tn144c"
syn_top = "brevia2_top"
syn_project = "demo"
syn_tool = "diamond"
modules = {
"local" : [ "../../../top/brevia2_dk/vhdl" ],
}
target = "altera"
action = "synthesis"
syn_device = "ep3c25"
syn_grade = "c6"
syn_package = "f324"
syn_top = "cyclone3_top"
syn_project = "demo"
syn_tool = "quartus"
quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule = "../../../top/cyclone3_sk/module.tcl"
modules = {
"local" : [ "../../../top/cyclone3_sk/verilog" ],
}
target = "altera"
action = "synthesis"
syn_device = "ep3c25"
syn_grade = "c6"
syn_package = "f324"
syn_top = "cyclone3_top"
syn_project = "demo"
syn_tool = "quartus"
quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule = "../../../top/cyclone3_sk/module.tcl"
modules = {
"local" : [ "../../../top/cyclone3_sk/vhdl" ],
}
target = "microsemi"
action = "synthesis"
syn_device = "a3p250"
syn_grade = "-2"
syn_package = "208 pqfp"
syn_top = "proasic3_top"
syn_project = "demo"
syn_tool = "libero"
modules = {
"local" : [ "../../../top/proasic3_sk/verilog" ],
}
target = "microsemi"
action = "synthesis"
syn_device = "a3p250"
syn_grade = "-2"
syn_package = "208 pqfp"
syn_top = "proasic3_top"
syn_project = "demo"
syn_tool = "libero"
modules = {
"local" : [ "../../../top/proasic3_sk/vhdl" ],
}
......@@ -4,12 +4,11 @@ action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "half2"
syn_project = "half2.xise"
syn_top = "spec_top"
syn_project = "demo.xise"
syn_tool = "ise"
files = [
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
modules = {
"local" : [ "../../../top/spec_v4/verilog" ],
}
......@@ -4,9 +4,11 @@ action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "myfilter"
syn_project = "myfilter.xise"
syn_top = "spec_top"
syn_project = "demo.xise"
syn_tool = "ise"
files = ["../../../modules/fir/myfilter.vhd"]
modules = {
"local" : [ "../../../top/spec_v4/vhdl" ],
}
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "demo"
syn_tool = "planahead"
modules = {
"local" : [ "../../../top/spec_v4/verilog" ],
}
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "demo"
syn_tool = "planahead"
modules = {
"local" : [ "../../../top/spec_v4/vhdl" ],
}
files = [
"counter_tb.v",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------
// Design : Simple testbench for an 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module counter_tb();
// Declare inputs as regs and outputs as wires
reg clock, clear, count;
wire [7:0] Q;
// Initialize all variables
initial begin
$dumpfile("counter_tb.vcd");
$dumpvars(0,counter_tb);
$display ("time\t clock clear count Q");
$monitor ("%g\t %b %b %b %b",
$time, clock, clear, count, Q);
clock = 1; // initial value of clock
clear = 0; // initial value of clear
count = 0; // initial value of count enable
#5 clear = 1; // Assert the clear signal
#10 clear = 0; // De-assert clear signal
#10 count = 1; // Start count
#2000 count = 0; // De-assert count enable
#5 $finish; // Terminate simulation
end
// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
counter U_counter (
clock,
clear,
count,
Q
);
endmodule
files = [
"counter_tb.vhd",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
----------------------------------------------------------
-- Design : Simple testbench for an 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity counter_tb is -- entity declaration
end counter_tb;
-----------------------------------------------------------------------
architecture testbench of counter_tb is
component counter
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal t_clock: std_logic;
signal t_clear: std_logic;
signal t_count: std_logic;
signal t_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter port map (t_clock, t_clear, t_count, t_Q);
process
begin
t_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
t_clock <= '1';
wait for 5 ns;
end process;
process
begin
t_clear <= '1'; -- start counting
t_count <= '1';
wait for 50 ns;
t_clear <= '0'; -- clear output
wait for 1000 ns;
report "Testbench of Adder completed successfully!"
severity note;
wait;
end process;
end testbench;
----------------------------------------------------------------
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "led_o_0" SITE "46" ;
LOCATE COMP "led_o_1" SITE "45" ;
LOCATE COMP "led_o_2" SITE "44" ;
LOCATE COMP "led_o_3" SITE "43" ;
LOCATE COMP "led_o_4" SITE "40" ;
LOCATE COMP "led_o_5" SITE "39" ;
LOCATE COMP "led_o_6" SITE "38" ;
LOCATE COMP "led_o_7" SITE "37" ;
LOCATE COMP "clear_i" SITE "50" ;
LOCATE COMP "count_i" SITE "53" ;
LOCATE COMP "clock_i" SITE "21" ;
LOCATE COMP "clken_o" SITE "22" ;
files = [
"brevia2_top.v",
"../brevia2_top.lpf",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------
// Design : Counter verilog top module, Lattice Brevia2
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module brevia2_top (
clear_i,
count_i,
clock_i,
clken_o,
led_o
);
input clear_i, count_i, clock_i;
output clken_o;
output [7:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign clken_o = 1;
assign s_clear = ~clear_i;
assign s_count = ~count_i;
assign led_o[7:0] = ~s_Q[7:0];
endmodule
files = [
"brevia2_top.vhd",
"../brevia2_top.lpf",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
----------------------------------------------------------
-- Design : Counter VHDL top module, Lattice Brevia2
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity brevia2_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
clken_o: out std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end brevia2_top;
----------------------------------------------------------
architecture structure of brevia2_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
clken_o <= '1';
s_clear <= not clear_i;
s_count <= not count_i;
led_o <= not s_Q;
end architecture structure;
----------------------------------------------------------------
set module [lindex $quartus(args) 0]
if [string match "quartus_map" $module] {
# Include commands here that are run
# after analysis and synthesis
post_message "Running after analysis & synthesis"
}
if [string match "quartus_fit" $module] {
# Include commands here that are run
# after fitter (Place & Route)
post_message "Running after place & route"
}
if [string match "quartus_asm" $module] {
# Include commands here that are run
# after assembler (Generate programming files)
post_message "Running after timing analysis"
}
if [string match "quartus_tan" $module] {
# Include commands here that are run
# after timing analysis
post_message "Running after timing analysis"
}
post_message "Assigning pinout"
# Load Quartus II Tcl Project package
package require ::quartus::project
project_open -revision demo demo
set_location_assignment PIN_F1 -to clear_i
set_location_assignment PIN_F2 -to count_i
set_location_assignment PIN_B9 -to clock_i
set_location_assignment PIN_N9 -to led_o[3]
set_location_assignment PIN_N12 -to led_o[2]
set_location_assignment PIN_P12 -to led_o[1]
set_location_assignment PIN_P13 -to led_o[0]
# Commit assignments
export_assignments
project_close
files = [
"cyclone3_top.v",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------------------
// Design : Counter verilog top module, Altera CycloneIII Starter Kit
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------------------
module cyclone3_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [3:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = ~clear_i;
assign s_count = ~count_i;
assign led_o[3:0] = ~s_Q[7:4];
endmodule
files = [
"cyclone3_top.vhd",
]
modules = {
"local" : [ ],
}
----------------------------------------------------------------------
-- Design : Counter VHDL top module, Altera CycloneIII Starter Kit
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cyclone3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end cyclone3_top;
----------------------------------------------------------------------
architecture structure of cyclone3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
# Microsemi Physical design constraints file
# Family: ProASIC3 , Die: A3P250 , Package: 208 PQFP , Speed grade: -2
#
# IO banks setting
#
set_iobank Bank3 -vcci 3.30 -fixed no
set_iobank Bank2 -vcci 3.30 -fixed no
set_iobank Bank1 -vcci 3.30 -fixed no
set_iobank Bank0 -vcci 3.30 -fixed no
#
# I/O constraints
#
set_io led_o\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 63 -fixed yes
set_io led_o\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 61 -fixed yes
set_io led_o\[2\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 60 -fixed yes
set_io led_o\[3\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 59 -fixed yes
set_io led_o\[4\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 58 -fixed yes
set_io led_o\[5\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 57 -fixed yes
set_io led_o\[6\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 56 -fixed yes
set_io led_o\[7\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 55 -fixed yes
set_io clear_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 68 -fixed yes
set_io count_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 67 -fixed yes
# 40MHz clock
set_io clock_i -iostd LVTTL -REGISTER No -RES_PULL None -pinname 26 -fixed yes
# Top Level Design Parameters
# Clocks
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top
# Other Constraints
files = [
"proasic3_top.v",
"../proasic3_top.pdc",
"../proasic3_top.sdc",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//---------------------------------------------------------------------
// Design : Counter verilog top module, Microsemi ProASIC3 Starter Kit
// Author : Javier D. Garcia-Lasheras
//---------------------------------------------------------------------
module proasic3_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [7:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = clear_i;
assign s_count = count_i;
assign led_o[7:0] = s_Q[7:0];
endmodule
files = [
"proasic3_top.vhd",
"../proasic3_top.pdc",
"../proasic3_top.sdc",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, Microsemi ProASIC3 Starter Kit
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity proasic3_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end proasic3_top;
-----------------------------------------------------------------------
architecture structure of proasic3_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= clear_i;
s_count <= count_i;
led_o <= s_Q;
end architecture structure;
----------------------------------------------------------------
NET "CLOCK_I" LOC = H12;
NET "CLOCK_I" IOSTANDARD = "LVCMOS18";
NET "COUNT_I" LOC = C22;
NET "COUNT_I" IOSTANDARD = "LVCMOS18";
NET "CLEAR_I" LOC = D21;
NET "CLEAR_I" IOSTANDARD = "LVCMOS18";
NET "LED_O[0]" LOC = G19;
NET "LED_O[0]" IOSTANDARD = "LVCMOS18";
NET "LED_O[1]" LOC = F20;
NET "LED_O[1]" IOSTANDARD = "LVCMOS18";
NET "LED_O[2]" LOC = F18;
NET "LED_O[2]" IOSTANDARD = "LVCMOS18";
NET "LED_O[3]" LOC = C20;
NET "LED_O[3]" IOSTANDARD = "LVCMOS18";
files = [ "spec_top.v", "../spec_top.ucf" ]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//---------------------------------------------------------------------
// Design : Counter verilog top module, SPEC (Simple PCIe Carrier)
// Author : Javier D. Garcia-Lasheras
//---------------------------------------------------------------------
module spec_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [3:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = ~clear_i;
assign s_count = ~count_i;
assign led_o[3:0] = ~s_Q[7:4];
endmodule
files = [ "spec_top.vhd", "../spec_top.ucf" ]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier)
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end spec_top;
-----------------------------------------------------------------------
architecture structure of spec_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
// Combined half-band filter and decimator
// See concept1.eps for general DSP idea
// See actual2.eps for graphical DSP representation
// Half-band filter configuration is
// -1 + 9 z^{-2} + 16 z^{-3} + 9 z^{-4} - 1 z^{-6}
// Decimation is controlled by the ab input, which _must_
// be clk/2. Output d gives a results when ab is low, and
// b results when ab is high. b results are delayed one
// cycle, corresponding to something like simultaneous
// sampling at the input.
// See actual2.eps
// Total 5 cycle latency for a, 6 cycles for b.
// Uses about 172 Slice Flip Flops and 174 4LUTs in Spartan-3.
// Larry Doolittle, LBNL, Oct. 2012
`timescale 1ns / 1ns
module half2(
input clk, // timespec 5.2 ns
input signed [15:0] a,
input signed [15:0] b,
input ab,
output signed [16:0] d
);
// buffer B one cycle, provides "simultaneous sampling"
reg [15:0] bb=0; always @(posedge clk) bb <= b;
// input switch
// left and right take their names from actual2.eps
wire signed [15:0] left = ab ? a : bb;
wire signed [15:0] right = ab ? bb : a;
wire signed [15:0] dl1;
reg_delay #(.dw(16), .len(3)) l1(.clk(clk),.gate(1'b1),.din(left),.dout(dl1));
wire signed [15:0] dr1, dr2;
reg_delay #(.dw(16), .len(2)) r1(.clk(clk),.gate(1'b1),.din(right),.dout(dr1));
reg_delay #(.dw(16), .len(4)) r2(.clk(clk),.gate(1'b1),.din(dr1), .dout(dr2));
`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x : {x[old],{new{~x[old]}}})
reg signed [16:0] s1=0, s2=0;
reg signed [20:0] m9=0;
reg signed [21:0] s3=0, s4=0;
always @(posedge clk) begin
s1 <= right + dr1;
s2 <= right + dr2;
m9 <= s1 + (s1<<<3);
s3 <= m9 + (dl1<<<4) + 8; // un-bias the truncation step
s4 <= s3 - s2;
end
wire signed [17:0] penult = s4[21:4]; // truncate 4 lsb
assign d = `SAT(penult,17,16); // clip 1 msb
endmodule
`timescale 1ns / 1ns
// sine-based testing of pass band on channel b is quite stringent:
// reference sine wave has no phase shift (execpt for compensation of
// the pipeline delay), and a small amplitude change (predicatble from
// theory for the non-DC input). Only +/-1 bit error is allowed, with
// almost no bias. rms error should in principle be 1/sqrt(12) = 0.29,
// we demand it be less than 0.33.
module half2_tb;
reg clk;
reg tracea=0,traceb=0;
reg peak_fail=0, avg_fail=0, rms_fail=0, fail=0;
integer cc, nsamp=0, offbyone=0, sum=0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("half2.vcd");
$dumpvars(5,half2_tb);
end
if ($test$plusargs("tracea")) tracea=1;
if ($test$plusargs("traceb")) traceb=1;
for (cc=0; cc<140; cc=cc+1) begin
clk=0; #5;
clk=1; #5;
end
rms_fail = offbyone > (nsamp+2)/3;
avg_fail = (sum > 4) || (sum < -4);
fail = peak_fail | avg_fail | rms_fail;
$display("x %d %d %d %d %s",nsamp,offbyone,sum,peak_fail,fail?"FAIL":"PASS");
$finish();
end
reg signed [15:0] ina=0, inb=0, sine=0;
reg signed [16:0] sineref=0;
reg ing=0;
integer noise;
integer nseed=1234;
reg ab=0;
always @(posedge clk) begin
ab <= ~ab;
sine = $floor(30000.0*$sin((cc )*0.1596)+0.5);
sineref = $floor(59992.8*$sin((cc-6)*0.1596)+0.5);
ina <= (cc==4 || cc==17) ? 1024 : 0;
//inb <= (cc>30) ? 28000 : -28000;
inb <= sine;
end
wire signed [16:0] outd;
half2 dut(.clk(clk), .a(ina), .b(inb), .ab(ab), .d(outd));
reg fault;
always @(negedge clk) begin
fault=0;
if (ab && cc>10) begin
nsamp = nsamp+1;
sum = sum + outd - sineref;
if (outd!=sineref) offbyone=offbyone+1;
fault = (outd>sineref+1) || (outd<sineref-1);
if (fault) peak_fail=1;
end
if ((tracea && (ab==0)) || (traceb && (ab==1)))
$display("%d %d %d %d %d %d", ab, ina, inb, outd, sineref, fault);
end
endmodule
// Combined half-band filter and decimator
// See concept1.eps for general DSP idea
// See actual3.eps for graphical DSP representation
// Half-band filter configuration is
// -1 + 9 z^{-2} + 16 z^{-3} + 9 z^{-4} - 1 z^{-6}
// This version set up for input streams that are already
// two-channel interleaved..
// Decimation is controlled by the ab input, which _must_
// be clk/4. Output d gives a results when ab is low, and
// b results when ab is high. b results are delayed one
// cycle, corresponding to something like simultaneous
// sampling at the input.
// Total 5 cycle latency for a, 6 cycles for b.
// Uses about 172 Slice Flip Flops and 174 4LUTs in Spartan-3.
// Larry Doolittle, LBNL, Oct. 2012
`timescale 1ns / 1ns
module half3(
input clk, // timespec 5.2 ns
input signed [15:0] a,
input signed [15:0] b,
input ab,
output signed [16:0] d
);
// buffer B two cycles, provides "simultaneous sampling"
reg [15:0] b1=0; always @(posedge clk) b1 <= b;
reg [15:0] bb=0; always @(posedge clk) bb <= b1;
// input switch
// left and right take their names from actual3.eps
wire signed [15:0] left = ab ? a : bb;
wire signed [15:0] right = ab ? bb : a;
wire signed [15:0] dl1;
reg_delay #(.dw(16), .len(6)) l1(.clk(clk),.gate(1'b1),.din(left),.dout(dl1));
wire signed [15:0] dr1, dr2;
reg_delay #(.dw(16), .len(4)) r1(.clk(clk),.gate(1'b1),.din(right),.dout(dr1));
reg_delay #(.dw(16), .len(8)) r2(.clk(clk),.gate(1'b1),.din(dr1), .dout(dr2));
`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x : {x[old],{new{~x[old]}}})
reg signed [16:0] s1=0, s2=0;
reg signed [20:0] m9=0, m9d=0, m9dd=0;
reg signed [21:0] s3=0, s4=0;
always @(posedge clk) begin
s1 <= right + dr1;
s2 <= right + dr2;
m9 <= s1 + (s1<<<3);
m9d <= m9;
m9dd <= m9d;
s3 <= m9dd + (dl1<<<4) + 8; // un-bias the truncation step
s4 <= s3 - s2;
end
wire signed [17:0] penult = s4[21:4]; // truncate 4 lsb
assign d = `SAT(penult,17,16); // clip 1 msb
endmodule
`timescale 1ns / 1ns
// sine-based testing of pass band on channel b is quite stringent:
// reference sine wave has no phase shift (execpt for compensation of
// the pipeline delay), and a small amplitude change (predicatble from
// theory for the non-DC input). Only +/-1 bit error is allowed, with
// almost no bias. rms error should in principle be 1/sqrt(12) = 0.29,
// we demand it be less than 0.33.
module half3_tb;
reg clk;
reg tracex=0,tracea=0,traceb=0;
reg peak_fail=0, avg_fail=0, rms_fail=0, fail=0;
integer cc, nsamp=0, offbyone=0, sum=0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("half3.vcd");
$dumpvars(5,half3_tb);
end
if ($test$plusargs("tracex")) tracex=1;
if ($test$plusargs("tracea")) tracea=1;
if ($test$plusargs("traceb")) traceb=1;
for (cc=0; cc<140; cc=cc+1) begin
clk=0; #5;
clk=1; #5;
end
rms_fail = offbyone > (nsamp+2)/3;
avg_fail = (sum > 4) || (sum < -4);
fail = peak_fail | avg_fail | rms_fail;
$display("x %d %d %d %d %s",nsamp,offbyone,sum,peak_fail,fail?"FAIL":"PASS");
$finish();
end
reg signed [15:0] ina=0, inb=0, sine=0;
reg signed [16:0] sineref=0;
reg ing=0;
integer noise;
integer nseed=1234;
reg [1:0] abc=0;
wire ab=abc[1];
wire cs=abc[0]; // cos vs. sin on a and b inputs
always @(posedge clk) begin
abc <= abc+1;
sine = $floor(30000.0*$sin((cc )*0.0798)+0.5);
sineref = $floor(59992.8*$sin((cc-10)*0.0798)+0.5);
ina <= (cc==4 || cc==17 || cc==30 || cc==43) ? 1024 : 0;
//inb <= (cc>30) ? 28000 : -28000;
inb <= cs ? sine : 0;
end
wire signed [16:0] outd;
half3 dut(.clk(clk), .a(ina), .b(inb), .ab(ab), .d(outd));
reg fault;
always @(negedge clk) begin
fault=0;
if ((abc==0) && (cc>16)) begin
nsamp = nsamp+1;
sum = sum + outd - sineref;
if (outd!=sineref) offbyone=offbyone+1;
fault = (outd>sineref+1) || (outd<sineref-1);
if (fault) peak_fail=1;
end
if (tracex | (tracea & (ab==0)) | (traceb & (abc==0)))
$display("%d %d %d %d %d %d", abc, ina, inb, outd, sineref, outd-sineref);
end
endmodule
`timescale 1ns / 1ns
module reg_delay(clk, gate, din, dout);
parameter dw=16;
parameter len=4;
input clk;
input gate;
input [dw-1:0] din;
output [dw-1:0] dout;
// len clocks of delay. Xilinx should turn this into
// dw*floor((len+15)/16)
// SRL16 shift registers, since there are no resets.
generate if (len > 1) begin: usual
reg [dw*len-1:0] shifter=0;
always @(posedge clk) if (gate) shifter <= {shifter[dw*len-1-dw:0],din};
assign dout = shifter[dw*len-1:dw*len-dw];
end else if (len > 0) begin: degen1
reg [dw*len-1:0] shifter=0;
always @(posedge clk) if (gate) shifter <= din;
assign dout = shifter[dw*len-1:dw*len-dw];
end else begin: degen0
assign dout = din;
end
endgenerate
endmodule
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity myfilter is
port (
clk : in std_logic;
rst : in std_logic;
sig_in : in signed(15 downto 0);
sig_out : out signed(15 downto 0)
);
end entity;
architecture Direct_Form_I_Transposed of myfilter is
-- This file has been generated with Libre-FDATool
-- Creation Time: 2014-04-26 01:36
-- Z^-1 delay blocks
type zb_array is array (0 to 6) of signed(30 downto 0);
signal zb, zb_next: zb_array;
-- Filter constants
type b_array is array (0 to 7) of signed(15 downto 0);
signal b: b_array;
-- Filter Adders
type sum_b_array is array (0 to 6) of signed(30 downto 0);
signal sb: sum_b_array;
-- Filter Products
type product_b_array is array (0 to 7) of signed(30 downto 0);
signal pb: product_b_array;
type product_b_temp_array is array (0 to 7) of signed(31 downto 0);
signal pb_temp: product_b_temp_array;
-- Feedback loop accumulator
signal v: signed(15 downto 0);
-- Begin Architecture
begin
-- Assign Coefficients
b(0) <= "0000111000100010"; -- 0.110401
b(1) <= "0000111110110011"; -- 0.122661
b(2) <= "0001000011001101"; -- 0.131255
b(3) <= "0001000101011110"; -- 0.135682
b(4) <= "0001000101011110"; -- 0.135682
b(5) <= "0001000011001101"; -- 0.131255
b(6) <= "0000111110110011"; -- 0.122661
b(7) <= "0000111000100010"; -- 0.110401
----------------------------------
-- Sequential logic description --
----------------------------------
-- Sequential delay chain for the B block
seq_b_block: for x in 0 to 6 generate
reg_b: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
zb(x) <= (others => '0');
else
zb(x) <= zb_next(x);
end if;
end if;
end process reg_b;
end generate seq_b_block;
----------------------------------
-- Processing logic description --
----------------------------------
-- Bypassing the A processing block
v <= sig_in;
-- Processing block for the Filter structure B side
process_b_block: for n in 0 to 7 generate
-- Calculate products being generated
pb_temp(n) <= v * b(n);
pb(n) <= pb_temp(n)(30 downto 0);
-- Calculate sums being generated
add_b_block: if (n < 7) generate
sb(n) <= pb(n) + zb(n);
end generate add_b_block;
-- Calculate values for zb_next
-- ... those halfway in the loop
mid_b_tap: if (n < 6) generate
zb_next(n) <= sb(n+1);
end generate mid_b_tap;
-- ... final structure
final_b_tap: if (n = 6) generate
zb_next(n) <= pb(n+1);
end generate final_b_tap;
end generate process_b_block;
-- Convert Fixed Point to sig_out from sb(0)
sig_out(15 downto 15) <= sb(0)(30 downto 30);
sig_out(14 downto 0) <= sb(0)(29 downto 15);
end Direct_Form_I_Transposed;
-- This file has been generated with Libre-FDATool
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
ENTITY tb_myfilter IS
END tb_myfilter;
ARCHITECTURE behavior OF tb_myfilter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT myfilter
PORT(
clk: IN std_logic;
rst: IN std_logic;
sig_in: IN signed(15 downto 0);
sig_out: OUT signed(15 downto 0)
);
END COMPONENT;
-- Signal Declaration
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal sig_in : signed(15 downto 0);
signal sig_out : signed(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: myfilter PORT MAP (
clk => clk,
rst => rst,
sig_in => sig_in,
sig_out => sig_out
);
clk_process : process
begin
clk <= '1';
wait for 25 ns;
clk <= '0';
wait for 25 ns;
end process;
stimulus_process : process
begin
sig_in <= (others => '0');
rst <= '1'; wait for 100 ns;
rst <= '0'; wait for 125 ns;
wait for 50 ns; sig_in <= "0000000000000000"; -- -0.000000
wait for 50 ns; sig_in <= "0000000000000101"; -- 0.000157
wait for 50 ns; sig_in <= "0000000000010101"; -- 0.000630
wait for 50 ns; sig_in <= "0000000000101110"; -- 0.001417
wait for 50 ns; sig_in <= "0000000001010011"; -- 0.002518
wait for 50 ns; sig_in <= "0000000010000001"; -- 0.003935
wait for 50 ns; sig_in <= "0000000010111010"; -- 0.005666
wait for 50 ns; sig_in <= "0000000011111101"; -- 0.007712
wait for 50 ns; sig_in <= "0000000101001010"; -- 0.010073
wait for 50 ns; sig_in <= "0000000110100010"; -- 0.012748
wait for 50 ns; sig_in <= "0000001000000100"; -- 0.015737
wait for 50 ns; sig_in <= "0000001001110000"; -- 0.019040
wait for 50 ns; sig_in <= "0000001011100110"; -- 0.022657
wait for 50 ns; sig_in <= "0000001101100111"; -- 0.026587
wait for 50 ns; sig_in <= "0000001111110010"; -- 0.030830
wait for 50 ns; sig_in <= "0000010010000111"; -- 0.035384
wait for 50 ns; sig_in <= "0000010100100111"; -- 0.040249
wait for 50 ns; sig_in <= "0000010111010000"; -- 0.045424
wait for 50 ns; sig_in <= "0000011010000100"; -- 0.050907
wait for 50 ns; sig_in <= "0000011101000010"; -- 0.056697
wait for 50 ns; sig_in <= "0000100000001010"; -- 0.062791
wait for 50 ns; sig_in <= "0000100011011011"; -- 0.069188
wait for 50 ns; sig_in <= "0000100110110111"; -- 0.075884
wait for 50 ns; sig_in <= "0000101010011100"; -- 0.082877
wait for 50 ns; sig_in <= "0000101110001010"; -- 0.090163
wait for 50 ns; sig_in <= "0000110010000011"; -- 0.097738
wait for 50 ns; sig_in <= "0000110110000100"; -- 0.105597
wait for 50 ns; sig_in <= "0000111010001111"; -- 0.113736
wait for 50 ns; sig_in <= "0000111110100011"; -- 0.122148
wait for 50 ns; sig_in <= "0001000010111111"; -- 0.130828
wait for 50 ns; sig_in <= "0001000111100100"; -- 0.139767
wait for 50 ns; sig_in <= "0001001100010001"; -- 0.148959
wait for 50 ns; sig_in <= "0001010001000110"; -- 0.158395
wait for 50 ns; sig_in <= "0001010110000011"; -- 0.168065
wait for 50 ns; sig_in <= "0001011011000111"; -- 0.177959
wait for 50 ns; sig_in <= "0001100000010011"; -- 0.188065
wait for 50 ns; sig_in <= "0001100101100100"; -- 0.198372
wait for 50 ns; sig_in <= "0001101010111100"; -- 0.208865
wait for 50 ns; sig_in <= "0001110000011010"; -- 0.219531
wait for 50 ns; sig_in <= "0001110101111100"; -- 0.230354
wait for 50 ns; sig_in <= "0001111011100100"; -- 0.241318
wait for 50 ns; sig_in <= "0010000001001111"; -- 0.252404
wait for 50 ns; sig_in <= "0010000110111101"; -- 0.263594
wait for 50 ns; sig_in <= "0010001100101111"; -- 0.274866
wait for 50 ns; sig_in <= "0010010010100010"; -- 0.286200
wait for 50 ns; sig_in <= "0010011000010111"; -- 0.297573
wait for 50 ns; sig_in <= "0010011110001100"; -- 0.308959
wait for 50 ns; sig_in <= "0010100100000001"; -- 0.320334
wait for 50 ns; sig_in <= "0010101001110100"; -- 0.331670
wait for 50 ns; sig_in <= "0010101111100101"; -- 0.342938
wait for 50 ns; sig_in <= "0010110101010011"; -- 0.354109
wait for 50 ns; sig_in <= "0010111010111101"; -- 0.365151
wait for 50 ns; sig_in <= "0011000000100010"; -- 0.376032
wait for 50 ns; sig_in <= "0011000110000000"; -- 0.386717
wait for 50 ns; sig_in <= "0011001011010110"; -- 0.397171
wait for 50 ns; sig_in <= "0011010000100100"; -- 0.407357
wait for 50 ns; sig_in <= "0011010101101000"; -- 0.417237
wait for 50 ns; sig_in <= "0011011010100000"; -- 0.426771
wait for 50 ns; sig_in <= "0011011111001100"; -- 0.435921
wait for 50 ns; sig_in <= "0011100011101010"; -- 0.444642
wait for 50 ns; sig_in <= "0011100111111000"; -- 0.452895
wait for 50 ns; sig_in <= "0011101011110110"; -- 0.460634
wait for 50 ns; sig_in <= "0011101111100001"; -- 0.467816
wait for 50 ns; sig_in <= "0011110010111001"; -- 0.474397
wait for 50 ns; sig_in <= "0011110101111011"; -- 0.480331
wait for 50 ns; sig_in <= "0011111000100111"; -- 0.485572
wait for 50 ns; sig_in <= "0011111010111011"; -- 0.490075
wait for 50 ns; sig_in <= "0011111100110101"; -- 0.493795
wait for 50 ns; sig_in <= "0011111110010011"; -- 0.496685
wait for 50 ns; sig_in <= "0011111111010101"; -- 0.498701
wait for 50 ns; sig_in <= "0011111111111001"; -- 0.499799
wait for 50 ns; sig_in <= "0011111111111110"; -- 0.499936
wait for 50 ns; sig_in <= "0011111111100001"; -- 0.499068
wait for 50 ns; sig_in <= "0011111110100011"; -- 0.497156
wait for 50 ns; sig_in <= "0011111101000001"; -- 0.494160
wait for 50 ns; sig_in <= "0011111010111010"; -- 0.490044
wait for 50 ns; sig_in <= "0011111000001101"; -- 0.484773
wait for 50 ns; sig_in <= "0011110100111001"; -- 0.478316
wait for 50 ns; sig_in <= "0011110000111110"; -- 0.470643
wait for 50 ns; sig_in <= "0011101100011010"; -- 0.461729
wait for 50 ns; sig_in <= "0011100111001100"; -- 0.451552
wait for 50 ns; sig_in <= "0011100001010101"; -- 0.440096
wait for 50 ns; sig_in <= "0011011010110011"; -- 0.427345
wait for 50 ns; sig_in <= "0011010011100111"; -- 0.413293
wait for 50 ns; sig_in <= "0011001011110000"; -- 0.397936
wait for 50 ns; sig_in <= "0011000011001110"; -- 0.381275
wait for 50 ns; sig_in <= "0010111010000001"; -- 0.363319
wait for 50 ns; sig_in <= "0010110000001011"; -- 0.344083
wait for 50 ns; sig_in <= "0010100101101011"; -- 0.323587
wait for 50 ns; sig_in <= "0010011010100011"; -- 0.301857
wait for 50 ns; sig_in <= "0010001110110100"; -- 0.278930
wait for 50 ns; sig_in <= "0010000010011111"; -- 0.254847
wait for 50 ns; sig_in <= "0001110101100101"; -- 0.229657
wait for 50 ns; sig_in <= "0001101000001010"; -- 0.203417
wait for 50 ns; sig_in <= "0001011010001110"; -- 0.176194
wait for 50 ns; sig_in <= "0001001011110100"; -- 0.148059
wait for 50 ns; sig_in <= "0000111100111111"; -- 0.119095
wait for 50 ns; sig_in <= "0000101101110001"; -- 0.089391
wait for 50 ns; sig_in <= "0000011110001111"; -- 0.059044
wait for 50 ns; sig_in <= "0000001110011011"; -- 0.028160
wait for 50 ns; sig_in <= "1111111110011001"; -- -0.003146
wait for 50 ns; sig_in <= "1111101110001101"; -- -0.034755
wait for 50 ns; sig_in <= "1111011101111100"; -- -0.066536
wait for 50 ns; sig_in <= "1111001101101001"; -- -0.098354
wait for 50 ns; sig_in <= "1110111101011010"; -- -0.130067
wait for 50 ns; sig_in <= "1110101101010011"; -- -0.161525
wait for 50 ns; sig_in <= "1110011101011010"; -- -0.192575
wait for 50 ns; sig_in <= "1110001101110011"; -- -0.223058
wait for 50 ns; sig_in <= "1101111110100100"; -- -0.252810
wait for 50 ns; sig_in <= "1101101111110010"; -- -0.281665
wait for 50 ns; sig_in <= "1101100001100100"; -- -0.309453
wait for 50 ns; sig_in <= "1101010011111110"; -- -0.336004
wait for 50 ns; sig_in <= "1101000111000110"; -- -0.361147
wait for 50 ns; sig_in <= "1100111011000010"; -- -0.384713
wait for 50 ns; sig_in <= "1100101111110111"; -- -0.406533
wait for 50 ns; sig_in <= "1100100101101010"; -- -0.426442
wait for 50 ns; sig_in <= "1100011100100010"; -- -0.444281
wait for 50 ns; sig_in <= "1100010100100010"; -- -0.459895
wait for 50 ns; sig_in <= "1100001101110000"; -- -0.473139
wait for 50 ns; sig_in <= "1100001000010000"; -- -0.483873
wait for 50 ns; sig_in <= "1100000100000111"; -- -0.491972
wait for 50 ns; sig_in <= "1100000001011000"; -- -0.497321
wait for 50 ns; sig_in <= "1100000000000110"; -- -0.499817
wait for 50 ns; sig_in <= "1100000000010101"; -- -0.499374
wait for 50 ns; sig_in <= "1100000010000110"; -- -0.495922
wait for 50 ns; sig_in <= "1100000101011011"; -- -0.489410
wait for 50 ns; sig_in <= "1100001010010110"; -- -0.479804
wait for 50 ns; sig_in <= "1100010000110110"; -- -0.467091
wait for 50 ns; sig_in <= "1100011000111100"; -- -0.451282
wait for 50 ns; sig_in <= "1100100010100111"; -- -0.432409
wait for 50 ns; sig_in <= "1100101101110100"; -- -0.410528
wait for 50 ns; sig_in <= "1100111010100001"; -- -0.385719
wait for 50 ns; sig_in <= "1101001000101010"; -- -0.358089
wait for 50 ns; sig_in <= "1101011000001100"; -- -0.327768
wait for 50 ns; sig_in <= "1101101001000000"; -- -0.294913
wait for 50 ns; sig_in <= "1101111011000010"; -- -0.259707
wait for 50 ns; sig_in <= "1110001110001010"; -- -0.222358
wait for 50 ns; sig_in <= "1110100010010000"; -- -0.183099
wait for 50 ns; sig_in <= "1110110111001101"; -- -0.142187
wait for 50 ns; sig_in <= "1111001100110110"; -- -0.099901
wait for 50 ns; sig_in <= "1111100011000011"; -- -0.056544
wait for 50 ns; sig_in <= "1111111001101000"; -- -0.012436
wait for 50 ns; sig_in <= "0000010000011011"; -- 0.032083
wait for 50 ns; sig_in <= "0000100111010000"; -- 0.076659
wait for 50 ns; sig_in <= "0000111101111010"; -- 0.120924
wait for 50 ns; sig_in <= "0001010100001110"; -- 0.164500
wait for 50 ns; sig_in <= "0001101001111111"; -- 0.207001
wait for 50 ns; sig_in <= "0001111111000000"; -- 0.248041
wait for 50 ns; sig_in <= "0010010011000100"; -- 0.287229
wait for 50 ns; sig_in <= "0010100101111111"; -- 0.324182
wait for 50 ns; sig_in <= "0010110111100100"; -- 0.358524
wait for 50 ns; sig_in <= "0011000111101000"; -- 0.389888
wait for 50 ns; sig_in <= "0011010101111111"; -- 0.417928
wait for 50 ns; sig_in <= "0011100010011110"; -- 0.442315
wait for 50 ns; sig_in <= "0011101100111011"; -- 0.462747
wait for 50 ns; sig_in <= "0011110101001110"; -- 0.478952
wait for 50 ns; sig_in <= "0011111011001111"; -- 0.490689
wait for 50 ns; sig_in <= "0011111110110110"; -- 0.497757
wait for 50 ns; sig_in <= "0100000000000000"; -- 0.499995
wait for 50 ns; sig_in <= "0011111110100111"; -- 0.497289
wait for 50 ns; sig_in <= "0011111010101010"; -- 0.489571
wait for 50 ns; sig_in <= "0011110100001001"; -- 0.476826
wait for 50 ns; sig_in <= "0011101011000100"; -- 0.459091
wait for 50 ns; sig_in <= "0011011111011110"; -- 0.436461
wait for 50 ns; sig_in <= "0011010001011101"; -- 0.409086
wait for 50 ns; sig_in <= "0011000001000111"; -- 0.377174
wait for 50 ns; sig_in <= "0010101110100110"; -- 0.340990
wait for 50 ns; sig_in <= "0010011010000010"; -- 0.300855
wait for 50 ns; sig_in <= "0010000011101010"; -- 0.257148
wait for 50 ns; sig_in <= "0001101011101011"; -- 0.210298
wait for 50 ns; sig_in <= "0001010010010101"; -- 0.160786
wait for 50 ns; sig_in <= "0000110111111000"; -- 0.109138
wait for 50 ns; sig_in <= "0000011100101000"; -- 0.055920
wait for 50 ns; sig_in <= "0000000000111001"; -- 0.001736
wait for 50 ns; sig_in <= "1111100100111110"; -- -0.052781
wait for 50 ns; sig_in <= "1111001001001111"; -- -0.106977
wait for 50 ns; sig_in <= "1110101101111111"; -- -0.160181
wait for 50 ns; sig_in <= "1110010011100110"; -- -0.211717
wait for 50 ns; sig_in <= "1101111010011011"; -- -0.260909
wait for 50 ns; sig_in <= "1101100010110001"; -- -0.307096
wait for 50 ns; sig_in <= "1101001100111111"; -- -0.349633
wait for 50 ns; sig_in <= "1100111001011001"; -- -0.387909
wait for 50 ns; sig_in <= "1100101000010001"; -- -0.421350
wait for 50 ns; sig_in <= "1100011001111001"; -- -0.449433
wait for 50 ns; sig_in <= "1100001110100000"; -- -0.471694
wait for 50 ns; sig_in <= "1100000110010010"; -- -0.487736
wait for 50 ns; sig_in <= "1100000001011010"; -- -0.497238
wait for 50 ns; sig_in <= "1100000000000001"; -- -0.499962
wait for 50 ns; sig_in <= "1100000010001011"; -- -0.495761
wait for 50 ns; sig_in <= "1100000111111001"; -- -0.484581
wait for 50 ns; sig_in <= "1100010001001011"; -- -0.466472
wait for 50 ns; sig_in <= "1100011101111010"; -- -0.441583
wait for 50 ns; sig_in <= "1100101110000000"; -- -0.410170
wait for 50 ns; sig_in <= "1101000001001111"; -- -0.372593
wait for 50 ns; sig_in <= "1101010111011001"; -- -0.329312
wait for 50 ns; sig_in <= "1101110000001100"; -- -0.280890
wait for 50 ns; sig_in <= "1110001011010001"; -- -0.227982
wait for 50 ns; sig_in <= "1110101000010010"; -- -0.171328
wait for 50 ns; sig_in <= "1111000110110010"; -- -0.111749
wait for 50 ns; sig_in <= "1111100110010101"; -- -0.050131
wait for 50 ns; sig_in <= "0000000110011100"; -- 0.012584
wait for 50 ns; sig_in <= "0000100110100111"; -- 0.075411
wait for 50 ns; sig_in <= "0001000110010100"; -- 0.137342
wait for 50 ns; sig_in <= "0001100101000011"; -- 0.197354
wait for 50 ns; sig_in <= "0010000010010001"; -- 0.254434
wait for 50 ns; sig_in <= "0010011101011111"; -- 0.307591
wait for 50 ns; sig_in <= "0010110110001101"; -- 0.355878
wait for 50 ns; sig_in <= "0011001011111111"; -- 0.398407
wait for 50 ns; sig_in <= "0011011110011001"; -- 0.434367
wait for 50 ns; sig_in <= "0011101101000101"; -- 0.463044
wait for 50 ns; sig_in <= "0011110111101110"; -- 0.483833
wait for 50 ns; sig_in <= "0011111110000101"; -- 0.496255
wait for 50 ns; sig_in <= "0011111111111111"; -- 0.499971
wait for 50 ns; sig_in <= "0011111101010101"; -- 0.494791
wait for 50 ns; sig_in <= "0011110110000111"; -- 0.480681
wait for 50 ns; sig_in <= "0011101010011000"; -- 0.457773
wait for 50 ns; sig_in <= "0011011010010011"; -- 0.426365
wait for 50 ns; sig_in <= "0011000110000111"; -- 0.386921
wait for 50 ns; sig_in <= "0010101110000111"; -- 0.340070
wait for 50 ns; sig_in <= "0010010010101111"; -- 0.286594
wait for 50 ns; sig_in <= "0001110100011100"; -- 0.227423
wait for 50 ns; sig_in <= "0001010011110001"; -- 0.163618
wait for 50 ns; sig_in <= "0000110001010101"; -- 0.096356
wait for 50 ns; sig_in <= "0000001101110010"; -- 0.026909
wait for 50 ns; sig_in <= "1111101001110011"; -- -0.043378
wait for 50 ns; sig_in <= "1111000110000101"; -- -0.113115
wait for 50 ns; sig_in <= "1110100011011001"; -- -0.180890
wait for 50 ns; sig_in <= "1110000010011010"; -- -0.245299
wait for 50 ns; sig_in <= "1101100011110111"; -- -0.304977
wait for 50 ns; sig_in <= "1101001000011000"; -- -0.358630
wait for 50 ns; sig_in <= "1100110000100111"; -- -0.405058
wait for 50 ns; sig_in <= "1100011101000110"; -- -0.443190
wait for 50 ns; sig_in <= "1100001110010010"; -- -0.472109
wait for 50 ns; sig_in <= "1100000100100100"; -- -0.491077
wait for 50 ns; sig_in <= "1100000000001111"; -- -0.499555
wait for 50 ns; sig_in <= "1100000001011011"; -- -0.497223
wait for 50 ns; sig_in <= "1100001000001100"; -- -0.483995
wait for 50 ns; sig_in <= "1100010100011110"; -- -0.460023
wait for 50 ns; sig_in <= "1100100110000010"; -- -0.425707
wait for 50 ns; sig_in <= "1100111100100101"; -- -0.381687
wait for 50 ns; sig_in <= "1101010111101001"; -- -0.328841
wait for 50 ns; sig_in <= "1101110110101001"; -- -0.268267
wait for 50 ns; sig_in <= "1110011000111101"; -- -0.201266
wait for 50 ns; sig_in <= "1110111101110011"; -- -0.129317
wait for 50 ns; sig_in <= "1111100100010101"; -- -0.054047
wait for 50 ns; sig_in <= "0000001011101011"; -- 0.022805
wait for 50 ns; sig_in <= "0000110010111010"; -- 0.099426
wait for 50 ns; sig_in <= "0001011001000101"; -- 0.173972
wait for 50 ns; sig_in <= "0001111101001111"; -- 0.244611
wait for 50 ns; sig_in <= "0010011110100000"; -- 0.309570
wait for 50 ns; sig_in <= "0010111100000000"; -- 0.367181
wait for 50 ns; sig_in <= "0011010100111101"; -- 0.415926
wait for 50 ns; sig_in <= "0011101000101100"; -- 0.454478
wait for 50 ns; sig_in <= "0011110110101010"; -- 0.481745
wait for 50 ns; sig_in <= "0011111110011010"; -- 0.496898
wait for 50 ns; sig_in <= "0011111111101101"; -- 0.499405
wait for 50 ns; sig_in <= "0011111010011001"; -- 0.489054
wait for 50 ns; sig_in <= "0011101110100101"; -- 0.465962
wait for 50 ns; sig_in <= "0011011100011101"; -- 0.430585
wait for 50 ns; sig_in <= "0011000100011110"; -- 0.383714
wait for 50 ns; sig_in <= "0010100111001010"; -- 0.326464
wait for 50 ns; sig_in <= "0010000101010000"; -- 0.260251
wait for 50 ns; sig_in <= "0001011111101000"; -- 0.186762
wait for 50 ns; sig_in <= "0000110111010000"; -- 0.107915
wait for 50 ns; sig_in <= "0000001101001110"; -- 0.025812
wait for 50 ns; sig_in <= "1111100010101010"; -- -0.057312
wait for 50 ns; sig_in <= "1110111000110000"; -- -0.139152
wait for 50 ns; sig_in <= "1110010000101100"; -- -0.217398
wait for 50 ns; sig_in <= "1101101011101000"; -- -0.289794
wait for 50 ns; sig_in <= "1101001010101001"; -- -0.354212
wait for 50 ns; sig_in <= "1100101110101111"; -- -0.408715
wait for 50 ns; sig_in <= "1100011000110001"; -- -0.451615
wait for 50 ns; sig_in <= "1100001001011101"; -- -0.481533
wait for 50 ns; sig_in <= "1100000001010100"; -- -0.497448
wait for 50 ns; sig_in <= "1100000000101001"; -- -0.498736
wait for 50 ns; sig_in <= "1100000111100101"; -- -0.485197
wait for 50 ns; sig_in <= "1100010101111111"; -- -0.457076
wait for 50 ns; sig_in <= "1100101011011111"; -- -0.415063
wait for 50 ns; sig_in <= "1101000111100010"; -- -0.360285
wait for 50 ns; sig_in <= "1101101001010101"; -- -0.294284
wait for 50 ns; sig_in <= "1110001111111001"; -- -0.218977
wait for 50 ns; sig_in <= "1110111010000100"; -- -0.136603
wait for 50 ns; sig_in <= "1111100110100101"; -- -0.049667
wait for 50 ns; sig_in <= "0000010100000010"; -- 0.039139
wait for 50 ns; sig_in <= "0001000001000010"; -- 0.127014
wait for 50 ns; sig_in <= "0001101100000111"; -- 0.211139
wait for 50 ns; sig_in <= "0010010011110110"; -- 0.288766
wait for 50 ns; sig_in <= "0010110110111100"; -- 0.357308
wait for 50 ns; sig_in <= "0011010100001100"; -- 0.414433
wait for 50 ns; sig_in <= "0011101010100100"; -- 0.458144
wait for 50 ns; sig_in <= "0011111001010001"; -- 0.486853
wait for 50 ns; sig_in <= "0011111111101110"; -- 0.499449
wait for 50 ns; sig_in <= "0011111101100111"; -- 0.495343
wait for 50 ns; sig_in <= "0011110010111100"; -- 0.474501
wait for 50 ns; sig_in <= "0011011111111111"; -- 0.437461
wait for 50 ns; sig_in <= "0011000101010010"; -- 0.385326
wait for 50 ns; sig_in <= "0010100011101101"; -- 0.319740
wait for 50 ns; sig_in <= "0001111100010110"; -- 0.242845
wait for 50 ns; sig_in <= "0001010000100000"; -- 0.157214
wait for 50 ns; sig_in <= "0000100001101011"; -- 0.065771
wait for 50 ns; sig_in <= "1111110001100001"; -- -0.028302
wait for 50 ns; sig_in <= "1111000001101101"; -- -0.121677
wait for 50 ns; sig_in <= "1110010011111110"; -- -0.210995
wait for 50 ns; sig_in <= "1101101001111111"; -- -0.292989
wait for 50 ns; sig_in <= "1101000101010101"; -- -0.364604
wait for 50 ns; sig_in <= "1100100111010111"; -- -0.423115
wait for 50 ns; sig_in <= "1100010001010010"; -- -0.466237
wait for 50 ns; sig_in <= "1100000011111111"; -- -0.492221
wait for 50 ns; sig_in <= "1100000000000010"; -- -0.499928
wait for 50 ns; sig_in <= "1100000101101100"; -- -0.488891
wait for 50 ns; sig_in <= "1100010100110100"; -- -0.459345
wait for 50 ns; sig_in <= "1100101100111100"; -- -0.412235
wait for 50 ns; sig_in <= "1101001101001110"; -- -0.349197
wait for 50 ns; sig_in <= "1101110100011110"; -- -0.272508
wait for 50 ns; sig_in <= "1110100001010001"; -- -0.185013
wait for 50 ns; sig_in <= "1111010001111010"; -- -0.090024
wait for 50 ns; sig_in <= "0000000100100000"; -- 0.008798
wait for 50 ns; sig_in <= "0000110111000101"; -- 0.107581
wait for 50 ns; sig_in <= "0001100111101000"; -- 0.202395
wait for 50 ns; sig_in <= "0010010100001011"; -- 0.289405
wait for 50 ns; sig_in <= "0010111010111001"; -- 0.365033
wait for 50 ns; sig_in <= "0011011010001011"; -- 0.426106
wait for 50 ns; sig_in <= "0011110000101001"; -- 0.469996
wait for 50 ns; sig_in <= "0011111101010100"; -- 0.494742
wait for 50 ns; sig_in <= "0011111111100100"; -- 0.499144
wait for 50 ns; sig_in <= "0011110111001101"; -- 0.482831
wait for 50 ns; sig_in <= "0011100100100000"; -- 0.446294
wait for 50 ns; sig_in <= "0011001000001000"; -- 0.390884
wait for 50 ns; sig_in <= "0010100011001110"; -- 0.318774
wait for 50 ns; sig_in <= "0001110111001111"; -- 0.232880
wait for 50 ns; sig_in <= "0001000110000001"; -- 0.136759
wait for 50 ns; sig_in <= "0000010001101001"; -- 0.034459
wait for 50 ns; sig_in <= "1111011100010110"; -- -0.069639
wait for 50 ns; sig_in <= "1110101000011100"; -- -0.171010
wait for 50 ns; sig_in <= "1101111000001111"; -- -0.265182
wait for 50 ns; sig_in <= "1101001101110111"; -- -0.347932
wait for 50 ns; sig_in <= "1100101011010001"; -- -0.415484
wait for 50 ns; sig_in <= "1100010010000101"; -- -0.464684
wait for 50 ns; sig_in <= "1100000011100000"; -- -0.493159
wait for 50 ns; sig_in <= "1100000000010010"; -- -0.499436
wait for 50 ns; sig_in <= "1100001000101100"; -- -0.483035
wait for 50 ns; sig_in <= "1100011100011010"; -- -0.444507
wait for 50 ns; sig_in <= "1100111010101010"; -- -0.385429
wait for 50 ns; sig_in <= "1101100010001000"; -- -0.308355
wait for 50 ns; sig_in <= "1110010001000011"; -- -0.216716
wait for 50 ns; sig_in <= "1111000101010010"; -- -0.114674
wait for 50 ns; sig_in <= "1111111100011100"; -- -0.006944
wait for 50 ns; sig_in <= "0000110011111011"; -- 0.101421
wait for 50 ns; sig_in <= "0001101001000110"; -- 0.205266
wait for 50 ns; sig_in <= "0010011001011001"; -- 0.299578
wait for 50 ns; sig_in <= "0011000010011011"; -- 0.379730
wait for 50 ns; sig_in <= "0011100010001010"; -- 0.441719
wait for 50 ns; sig_in <= "0011110110111110"; -- 0.482369
wait for 50 ns; sig_in <= "0011111111110000"; -- 0.499507
wait for 50 ns; sig_in <= "0011111011111101"; -- 0.492088
wait for 50 ns; sig_in <= "0011101011101010"; -- 0.460274
wait for 50 ns; sig_in <= "0011001111100110"; -- 0.405443
wait for 50 ns; sig_in <= "0010101001000010"; -- 0.330151
wait for 50 ns; sig_in <= "0001111001110111"; -- 0.238021
wait for 50 ns; sig_in <= "0001000100011001"; -- 0.133580
wait for 50 ns; sig_in <= "0000001011010010"; -- 0.022049
wait for 50 ns; sig_in <= "1111010001011101"; -- -0.090917
wait for 50 ns; sig_in <= "1110011001110111"; -- -0.199508
wait for 50 ns; sig_in <= "1101100111011001"; -- -0.298062
wait for 50 ns; sig_in <= "1100111100110000"; -- -0.381362
wait for 50 ns; sig_in <= "1100011100001101"; -- -0.444921
wait for 50 ns; sig_in <= "1100000111100100"; -- -0.485227
wait for 50 ns; sig_in <= "1100000000000001"; -- -0.499958
wait for 50 ns; sig_in <= "1100000110000101"; -- -0.488120
wait for 50 ns; sig_in <= "1100011001100010"; -- -0.450132
wait for 50 ns; sig_in <= "1100111001011100"; -- -0.387826
wait for 50 ns; sig_in <= "1101100100001010"; -- -0.304377
wait for 50 ns; sig_in <= "1110010111011110"; -- -0.204155
wait for 50 ns; sig_in <= "1111010000101001"; -- -0.092506
wait for 50 ns; sig_in <= "0000001100100100"; -- 0.024522
wait for 50 ns; sig_in <= "0001000111111100"; -- 0.140502
wait for 50 ns; sig_in <= "0001111111011111"; -- 0.248980
wait for 50 ns; sig_in <= "0010110000000011"; -- 0.343837
wait for 50 ns; sig_in <= "0011010110110111"; -- 0.419637
wait for 50 ns; sig_in <= "0011110001101001"; -- 0.471949
wait for 50 ns; sig_in <= "0011111110110010"; -- 0.497619
wait for 50 ns; sig_in <= "0011111101011011"; -- 0.494973
wait for 50 ns; sig_in <= "0011101101100010"; -- 0.463940
wait for 50 ns; sig_in <= "0011001111111011"; -- 0.406089
wait for 50 ns; sig_in <= "0010100110001011"; -- 0.324562
wait for 50 ns; sig_in <= "0001110010101010"; -- 0.223925
wait for 50 ns; sig_in <= "0000111000010010"; -- 0.109924
wait for 50 ns; sig_in <= "1111111010011101"; -- -0.010836
wait for 50 ns; sig_in <= "1110111100110011"; -- -0.131261
wait for 50 ns; sig_in <= "1110000010111110"; -- -0.244187
wait for 50 ns; sig_in <= "1101010000011111"; -- -0.342806
wait for 50 ns; sig_in <= "1100101000011010"; -- -0.421085
wait for 50 ns; sig_in <= "1100001101001111"; -- -0.474140
wait for 50 ns; sig_in <= "1100000000101111"; -- -0.498560
wait for 50 ns; sig_in <= "1100000011110001"; -- -0.492637
wait for 50 ns; sig_in <= "1100010110010001"; -- -0.456505
wait for 50 ns; sig_in <= "1100110111001110"; -- -0.392162
wait for 50 ns; sig_in <= "1101100100101011"; -- -0.303380
wait for 50 ns; sig_in <= "1110011011111010"; -- -0.195501
wait for 50 ns; sig_in <= "1111011001100010"; -- -0.075131
wait for 50 ns; sig_in <= "0000011001101111"; -- 0.050256
wait for 50 ns; sig_in <= "0001011000011110"; -- 0.172776
wait for 50 ns; sig_in <= "0010010001101111"; -- 0.284629
wait for 50 ns; sig_in <= "0011000001110110"; -- 0.378597
wait for 50 ns; sig_in <= "0011100101101001"; -- 0.448524
wait for 50 ns; sig_in <= "0011111010101111"; -- 0.489724
wait for 50 ns; sig_in <= "0011111111101010"; -- 0.499319
wait for 50 ns; sig_in <= "0011110011111100"; -- 0.476452
wait for 50 ns; sig_in <= "0011011000010001"; -- 0.422380
wait for 50 ns; sig_in <= "0010101110010011"; -- 0.340430
wait for 50 ns; sig_in <= "0001111000101111"; -- 0.235808
wait for 50 ns; sig_in <= "0000111011000010"; -- 0.115294
wait for 50 ns; sig_in <= "1111111001010000"; -- -0.013193
wait for 50 ns; sig_in <= "1110110111110000"; -- -0.141101
wait for 50 ns; sig_in <= "1101111010111110"; -- -0.259816
wait for 50 ns; sig_in <= "1101000111000011"; -- -0.361239
wait for 50 ns; sig_in <= "1100011111100100"; -- -0.438352
wait for 50 ns; sig_in <= "1100000111010100"; -- -0.485715
wait for 50 ns; sig_in <= "1100000000000100"; -- -0.499865
wait for 50 ns; sig_in <= "1100001010011101"; -- -0.479589
wait for 50 ns; sig_in <= "1100100101110111"; -- -0.426047
wait for 50 ns; sig_in <= "1101010000100001"; -- -0.342730
wait for 50 ns; sig_in <= "1110000111100011"; -- -0.235255
wait for 50 ns; sig_in <= "1111000111001011"; -- -0.111003
wait for 50 ns; sig_in <= "0000001010111100"; -- 0.021371
wait for 50 ns; sig_in <= "0001001110000110"; -- 0.152534
wait for 50 ns; sig_in <= "0010001011110110"; -- 0.273131
wait for 50 ns; sig_in <= "0010111111101110"; -- 0.374453
wait for 50 ns; sig_in <= "0011100101111011"; -- 0.449077
wait for 50 ns; sig_in <= "0011111011100111"; -- 0.491425
wait for 50 ns; sig_in <= "0011111111000101"; -- 0.498198
wait for 50 ns; sig_in <= "0011101111111101"; -- 0.468655
wait for 50 ns; sig_in <= "0011001111001110"; -- 0.404711
wait for 50 ns; sig_in <= "0010011111001001"; -- 0.310835
wait for 50 ns; sig_in <= "0001100011001101"; -- 0.193766
wait for 50 ns; sig_in <= "0000011111110001"; -- 0.062040
wait for 50 ns; sig_in <= "1111011001110011"; -- -0.074610
wait for 50 ns; sig_in <= "1110010110100011"; -- -0.205974
wait for 50 ns; sig_in <= "1101011011000101"; -- -0.322120
wait for 50 ns; sig_in <= "1100101011111101"; -- -0.414159
wait for 50 ns; sig_in <= "1100001100110101"; -- -0.474932
wait for 50 ns; sig_in <= "1100000000001110"; -- -0.499587
wait for 50 ns; sig_in <= "1100000111001011"; -- -0.485989
wait for 50 ns; sig_in <= "1100100001010100"; -- -0.434930
wait for 50 ns; sig_in <= "1101001100110000"; -- -0.350109
wait for 50 ns; sig_in <= "1110000110001101"; -- -0.237892
wait for 50 ns; sig_in <= "1111001001010010"; -- -0.106859
wait for 50 ns; sig_in <= "0000010000110100"; -- 0.032840
wait for 50 ns; sig_in <= "0001010111001011"; -- 0.170257
wait for 50 ns; sig_in <= "0010010110110010"; -- 0.294503
wait for 50 ns; sig_in <= "0011001010100100"; -- 0.395617
wait for 50 ns; sig_in <= "0011101110010001"; -- 0.465373
wait for 50 ns; sig_in <= "0011111110111110"; -- 0.497972
wait for 50 ns; sig_in <= "0011111011001010"; -- 0.490544
wait for 50 ns; sig_in <= "0011100011000010"; -- 0.443428
wait for 50 ns; sig_in <= "0010111000011011"; -- 0.360190
wait for 50 ns; sig_in <= "0001111110101010"; -- 0.247389
wait for 50 ns; sig_in <= "0000111010011010"; -- 0.114075
wait for 50 ns; sig_in <= "1111110001001101"; -- -0.028911
wait for 50 ns; sig_in <= "1110101001000100"; -- -0.169812
wait for 50 ns; sig_in <= "1101100111111111"; -- -0.296913
wait for 50 ns; sig_in <= "1100110011011100"; -- -0.399529
wait for 50 ns; sig_in <= "1100001111111011"; -- -0.468907
wait for 50 ns; sig_in <= "1100000000100001"; -- -0.498997
wait for 50 ns; sig_in <= "1100000110101010"; -- -0.487007
wait for 50 ns; sig_in <= "1100100001111101"; -- -0.433684
wait for 50 ns; sig_in <= "1101010000001111"; -- -0.343307
wait for 50 ns; sig_in <= "1110001101101001"; -- -0.223372
wait for 50 ns; sig_in <= "1111010101000000"; -- -0.083998
wait for 50 ns; sig_in <= "0000100000001110"; -- 0.062913
wait for 50 ns; sig_in <= "0001101000110011"; -- 0.204678
wait for 50 ns; sig_in <= "0010101000011010"; -- 0.328926
wait for 50 ns; sig_in <= "0011011001011100"; -- 0.424690
wait for 50 ns; sig_in <= "0011110111100000"; -- 0.483386
wait for 50 ns; sig_in <= "0011111111110011"; -- 0.499608
wait for 50 ns; sig_in <= "0011110001011111"; -- 0.471656
wait for 50 ns; sig_in <= "0011001101101100"; -- 0.401736
wait for 50 ns; sig_in <= "0010010111011110"; -- 0.295828
wait for 50 ns; sig_in <= "0001010011100100"; -- 0.163198
wait for 50 ns; sig_in <= "0000001000000000"; -- 0.015616
wait for 50 ns; sig_in <= "1110111011100100"; -- -0.133677
wait for 50 ns; sig_in <= "1101110101001011"; -- -0.271144
wait for 50 ns; sig_in <= "1100111011010011"; -- -0.384188
wait for 50 ns; sig_in <= "1100010011010011"; -- -0.462316
wait for 50 ns; sig_in <= "1100000000111101"; -- -0.498138
wait for 50 ns; sig_in <= "1100000110000110"; -- -0.488090
wait for 50 ns; sig_in <= "1100100010011001"; -- -0.432821
wait for 50 ns; sig_in <= "1101010011010111"; -- -0.337197
wait for 50 ns; sig_in <= "1110010100100010"; -- -0.209900
wait for 50 ns; sig_in <= "1111011111111010"; -- -0.062673
wait for 50 ns; sig_in <= "0000101110011110"; -- 0.090745
wait for 50 ns; sig_in <= "0001111000110010"; -- 0.235890
wait for 50 ns; sig_in <= "0010110111110010"; -- 0.358938
wait for 50 ns; sig_in <= "0011100101011001"; -- 0.448030
wait for 50 ns; sig_in <= "0011111101001010"; -- 0.494439
wait for 50 ns; sig_in <= "0011111100101001"; -- 0.493450
wait for 50 ns; sig_in <= "0011100011110010"; -- 0.444876
wait for 50 ns; sig_in <= "0010110100110100"; -- 0.353136
wait for 50 ns; sig_in <= "0001110100001011"; -- 0.226890
wait for 50 ns; sig_in <= "0000101000000100"; -- 0.078256
wait for 50 ns; sig_in <= "1111010111111001"; -- -0.078334
wait for 50 ns; sig_in <= "1110001011100001"; -- -0.227521
wait for 50 ns; sig_in <= "1101001010011111"; -- -0.354526
wait for 50 ns; sig_in <= "1100011011010101"; -- -0.446623
wait for 50 ns; sig_in <= "1100000010110110"; -- -0.494438
wait for 50 ns; sig_in <= "1100000011101000"; -- -0.492933
wait for 50 ns; sig_in <= "1100011101101110"; -- -0.441968
wait for 50 ns; sig_in <= "1101001110101010"; -- -0.346389
wait for 50 ns; sig_in <= "1110010001100111"; -- -0.215600
wait for 50 ns; sig_in <= "1111011111111010"; -- -0.062676
wait for 50 ns; sig_in <= "0000110001101000"; -- 0.096926
wait for 50 ns; sig_in <= "0001111110011011"; -- 0.246914
wait for 50 ns; sig_in <= "0010111110011000"; -- 0.371825
wait for 50 ns; sig_in <= "0011101010110101"; -- 0.458635
wait for 50 ns; sig_in <= "0011111111000011"; -- 0.498138
wait for 50 ns; sig_in <= "0011111000110100"; -- 0.485955
wait for 50 ns; sig_in <= "0011011000100111"; -- 0.423061
wait for 50 ns; sig_in <= "0010100001101011"; -- 0.315752
wait for 50 ns; sig_in <= "0001011001101000"; -- 0.175053
wait for 50 ns; sig_in <= "0000001000000000"; -- 0.015622
wait for 50 ns; sig_in <= "1110110101011000"; -- -0.145760
wait for 50 ns; sig_in <= "1101101010100010"; -- -0.291945
wait for 50 ns; sig_in <= "1100101111100000"; -- -0.407241
wait for 50 ns; sig_in <= "1100001010101100"; -- -0.479121
wait for 50 ns; sig_in <= "1100000000001101"; -- -0.499608
wait for 50 ns; sig_in <= "1100010001010100"; -- -0.466202
wait for 50 ns; sig_in <= "1100111100010100"; -- -0.382217
wait for 50 ns; sig_in <= "1101111100101011"; -- -0.256507
wait for 50 ns; sig_in <= "1111001011011111"; -- -0.102562
wait for 50 ns; sig_in <= "0000100000001101"; -- 0.062904
wait for 50 ns; sig_in <= "0001110001100010"; -- 0.221751
wait for 50 ns; sig_in <= "0010110110011111"; -- 0.356404
wait for 50 ns; sig_in <= "0011100111010101"; -- 0.451803
wait for 50 ns; sig_in <= "0011111110100010"; -- 0.497117
wait for 50 ns; sig_in <= "0011111001010110"; -- 0.487010
wait for 50 ns; sig_in <= "0011011000001110"; -- 0.422306
wait for 50 ns; sig_in <= "0010011110101110"; -- 0.309984
wait for 50 ns; sig_in <= "0001010011001100"; -- 0.162463
wait for 50 ns; sig_in <= "1111111110000110"; -- -0.003732
wait for 50 ns; sig_in <= "1110101001000100"; -- -0.169800
wait for 50 ns; sig_in <= "1101011101110100"; -- -0.316781
wait for 50 ns; sig_in <= "1100100101000000"; -- -0.427729
wait for 50 ns; sig_in <= "1100000101010010"; -- -0.489688
wait for 50 ns; sig_in <= "1100000010011100"; -- -0.495240
wait for 50 ns; sig_in <= "1100011100111110"; -- -0.443434
wait for 50 ns; sig_in <= "1101010001111011"; -- -0.339983
wait for 50 ns; sig_in <= "1110011011010011"; -- -0.196680
wait for 50 ns; sig_in <= "1111110000100110"; -- -0.030091
wait for 50 ns; sig_in <= "0001000111110110"; -- 0.140327
wait for 50 ns; sig_in <= "0010010110110010"; -- 0.294491
wait for 50 ns; sig_in <= "0011010100000000"; -- 0.414061
wait for 50 ns; sig_in <= "0011111000001001"; -- 0.484646
wait for 50 ns; sig_in <= "0011111110110000"; -- 0.497564
wait for 50 ns; sig_in <= "0011100110111001"; -- 0.450963
wait for 50 ns; sig_in <= "0010110011010001"; -- 0.350121
wait for 50 ns; sig_in <= "0001101001111100"; -- 0.206905
wait for 50 ns; sig_in <= "0000010011101011"; -- 0.038415
wait for 50 ns; sig_in <= "1110111010110111"; -- -0.135029
wait for 50 ns; sig_in <= "1101101010010101"; -- -0.292323
wait for 50 ns; sig_in <= "1100101011111101"; -- -0.414149
wait for 50 ns; sig_in <= "1100000111011111"; -- -0.485372
wait for 50 ns; sig_in <= "1100000001100100"; -- -0.496957
wait for 50 ns; sig_in <= "1100011011000100"; -- -0.447157
wait for 50 ns; sig_in <= "1101010000111111"; -- -0.341828
wait for 50 ns; sig_in <= "1110011100110010"; -- -0.193785
wait for 50 ns; sig_in <= "1111110101000110"; -- -0.021292
wait for 50 ns; sig_in <= "0001001110111100"; -- 0.154161
wait for 50 ns; sig_in <= "0010011110111111"; -- 0.310526
wait for 50 ns; sig_in <= "0011011011001000"; -- 0.427971
wait for 50 ns; sig_in <= "0011111011100111"; -- 0.491421
wait for 50 ns; sig_in <= "0011111100001011"; -- 0.492534
wait for 50 ns; sig_in <= "0011011100100110"; -- 0.430845
wait for 50 ns; sig_in <= "0010100000101111"; -- 0.313925
wait for 50 ns; sig_in <= "0001010000001000"; -- 0.156502
wait for 50 ns; sig_in <= "1111110101000100"; -- -0.021347
wait for 50 ns; sig_in <= "1110011011010001"; -- -0.196733
wait for 50 ns; sig_in <= "1101001110011001"; -- -0.346889
wait for 50 ns; sig_in <= "1100011000100000"; -- -0.452136
wait for 50 ns; sig_in <= "1100000000110001"; -- -0.498498
wait for 50 ns; sig_in <= "1100001010011101"; -- -0.479596
wait for 50 ns; sig_in <= "1100110100011100"; -- -0.397586
wait for 50 ns; sig_in <= "1101111001010111"; -- -0.262970
wait for 50 ns; sig_in <= "1111010000001110"; -- -0.093310
wait for 50 ns; sig_in <= "0000101101100101"; -- 0.089027
wait for 50 ns; sig_in <= "0010000101000001"; -- 0.259793
wait for 50 ns; sig_in <= "0011001010110011"; -- 0.396084
wait for 50 ns; sig_in <= "0011110101011110"; -- 0.479432
wait for 50 ns; sig_in <= "0011111111001010"; -- 0.498344
wait for 50 ns; sig_in <= "0011100110011000"; -- 0.449941
wait for 50 ns; sig_in <= "0010101110010100"; -- 0.340450
wait for 50 ns; sig_in <= "0001011110011101"; -- 0.184464
wait for 50 ns; sig_in <= "0000000001100100"; -- 0.003046
wait for 50 ns; sig_in <= "1110100100010100"; -- -0.179083
wait for 50 ns; sig_in <= "1101010011100001"; -- -0.336896
wait for 50 ns; sig_in <= "1100011010010111"; -- -0.448510
wait for 50 ns; sig_in <= "1100000000111001"; -- -0.498257
wait for 50 ns; sig_in <= "1100001010110011"; -- -0.478924
wait for 50 ns; sig_in <= "1100110110110111"; -- -0.392864
wait for 50 ns; sig_in <= "1101111111000110"; -- -0.251773
wait for 50 ns; sig_in <= "1111011001100001"; -- -0.075163
wait for 50 ns; sig_in <= "0000111001100000"; -- 0.112301
wait for 50 ns; sig_in <= "0010010001100001"; -- 0.284215
wait for 50 ns; sig_in <= "0011010101000101"; -- 0.416162
wait for 50 ns; sig_in <= "0011111010011110"; -- 0.489203
wait for 50 ns; sig_in <= "0011111100001111"; -- 0.492643
wait for 50 ns; sig_in <= "0011011001111100"; -- 0.425650
wait for 50 ns; sig_in <= "0010011000010100"; -- 0.297493
wait for 50 ns; sig_in <= "0001000000101011"; -- 0.126321
wait for 50 ns; sig_in <= "1111011111100100"; -- -0.063358
wait for 50 ns; sig_in <= "1110000010111111"; -- -0.244157
wait for 50 ns; sig_in <= "1100111000011101"; -- -0.389755
wait for 50 ns; sig_in <= "1100001010111000"; -- -0.478755
wait for 50 ns; sig_in <= "1100000001000110"; -- -0.497866
wait for 50 ns; sig_in <= "1100011100101101"; -- -0.443948
wait for 50 ns; sig_in <= "1101011001110100"; -- -0.324590
wait for 50 ns; sig_in <= "1110101111100100"; -- -0.157108
wait for 50 ns; sig_in <= "0000010001010111"; -- 0.033911
wait for 50 ns; sig_in <= "0001110000101111"; -- 0.220184
wait for 50 ns; sig_in <= "0010111111011100"; -- 0.373910
wait for 50 ns; sig_in <= "0011110001101000"; -- 0.471937
wait for 50 ns; sig_in <= "0011111111101001"; -- 0.499287
wait for 50 ns; sig_in <= "0011100111001011"; -- 0.451511
wait for 50 ns; sig_in <= "0010101011110001"; -- 0.335467
wait for 50 ns; sig_in <= "0001010110001111"; -- 0.168419
wait for 50 ns; sig_in <= "1111110011011110"; -- -0.024482
wait for 50 ns; sig_in <= "1110010010011101"; -- -0.213944
wait for 50 ns; sig_in <= "1101000010000100"; -- -0.370969
wait for 50 ns; sig_in <= "1100001110101100"; -- -0.471309
wait for 50 ns; sig_in <= "1100000000011000"; -- -0.499254
wait for 50 ns; sig_in <= "1100011001100001"; -- -0.450150
wait for 50 ns; sig_in <= "1101010110011010"; -- -0.331246
wait for 50 ns; sig_in <= "1110101101101110"; -- -0.160692
wait for 50 ns; sig_in <= "0000010010000000"; -- 0.035164
wait for 50 ns; sig_in <= "0001110011101000"; -- 0.225816
wait for 50 ns; sig_in <= "0011000011010000"; -- 0.381335
wait for 50 ns; sig_in <= "0011110100010001"; -- 0.477089
wait for 50 ns; sig_in <= "0011111110110100"; -- 0.497688
wait for 50 ns; sig_in <= "0011100001000010"; -- 0.439527
wait for 50 ns; sig_in <= "0010011111011111"; -- 0.311479
wait for 50 ns; sig_in <= "0001000100011011"; -- 0.133622
wait for 50 ns; sig_in <= "1111011110010010"; -- -0.065849
wait for 50 ns; sig_in <= "1101111101011010"; -- -0.255061
wait for 50 ns; sig_in <= "1100110001011001"; -- -0.403543
wait for 50 ns; sig_in <= "1100000110100101"; -- -0.487162
wait for 50 ns; sig_in <= "1100000100000011"; -- -0.492096
wait for 50 ns; sig_in <= "1100101010011010"; -- -0.417186
wait for 50 ns; sig_in <= "1101110011100101"; -- -0.274264
wait for 50 ns; sig_in <= "1111010011110010"; -- -0.086355
wait for 50 ns; sig_in <= "0000111011011000"; -- 0.115969
wait for 50 ns; sig_in <= "0010011001010111"; -- 0.299540
wait for 50 ns; sig_in <= "0011011110001110"; -- 0.434025
wait for 50 ns; sig_in <= "0011111110011101"; -- 0.496978
wait for 50 ns; sig_in <= "0011110100100011"; -- 0.477642
wait for 50 ns; sig_in <= "0011000001111111"; -- 0.378863
wait for 50 ns; sig_in <= "0001101110111111"; -- 0.216760
wait for 50 ns; sig_in <= "0000001001010011"; -- 0.018164
wait for 50 ns; sig_in <= "1110100001111010"; -- -0.183765
wait for 50 ns; sig_in <= "1101001010001101"; -- -0.355060
wait for 50 ns; sig_in <= "1100010001000100"; -- -0.466672
wait for 50 ns; sig_in <= "1100000000010010"; -- -0.499439
wait for 50 ns; sig_in <= "1100011010111010"; -- -0.447447
wait for 50 ns; sig_in <= "1101011100100101"; -- -0.319177
wait for 50 ns; sig_in <= "1110111010010001"; -- -0.136203
wait for 50 ns; sig_in <= "0000100100000010"; -- 0.070366
wait for 50 ns; sig_in <= "0010000111110000"; -- 0.265138
wait for 50 ns; sig_in <= "0011010100001110"; -- 0.414490
wait for 50 ns; sig_in <= "0011111100000111"; -- 0.492404
wait for 50 ns; sig_in <= "0011111000010110"; -- 0.485059
wait for 50 ns; sig_in <= "0011001001011010"; -- 0.393359
wait for 50 ns; sig_in <= "0001110111010001"; -- 0.232928
wait for 50 ns; sig_in <= "0000010000001001"; -- 0.031529
wait for 50 ns; sig_in <= "1110100110000011"; -- -0.175684
wait for 50 ns; sig_in <= "1101001011101001"; -- -0.352276
wait for 50 ns; sig_in <= "1100010000111011"; -- -0.466952
wait for 50 ns; sig_in <= "1100000000011100"; -- -0.499147
wait for 50 ns; sig_in <= "1100011101010011"; -- -0.442790
wait for 50 ns; sig_in <= "1101100010100011"; -- -0.307529
wait for 50 ns; sig_in <= "1111000100000000"; -- -0.117176
wait for 50 ns; sig_in <= "0000110000010110"; -- 0.094423
wait for 50 ns; sig_in <= "0010010100001010"; -- 0.289359
wait for 50 ns; sig_in <= "0011011101011011"; -- 0.432451
wait for 50 ns; sig_in <= "0011111110110010"; -- 0.497629
wait for 50 ns; sig_in <= "0011110010000011"; -- 0.472755
wait for 50 ns; sig_in <= "0010111001010101"; -- 0.361961
wait for 50 ns; sig_in <= "0001011110110000"; -- 0.185067
wait for 50 ns; sig_in <= "1111110010110000"; -- -0.025885
wait for 50 ns; sig_in <= "1110001001000001"; -- -0.232382
wait for 50 ns; sig_in <= "1100110101000001"; -- -0.396456
wait for 50 ns; sig_in <= "1100000110010011"; -- -0.487687
wait for 50 ns; sig_in <= "1100000101101100"; -- -0.488903
wait for 50 ns; sig_in <= "1100110011011101"; -- -0.399500
wait for 50 ns; sig_in <= "1110000111010100"; -- -0.235713
wait for 50 ns; sig_in <= "1111110001110010"; -- -0.027763
wait for 50 ns; sig_in <= "0001011111000100"; -- 0.185659
wait for 50 ns; sig_in <= "0010111010101010"; -- 0.364562
wait for 50 ns; sig_in <= "0011110011010010"; -- 0.475163
wait for 50 ns; sig_in <= "0011111110001000"; -- 0.496323
wait for 50 ns; sig_in <= "0011011000111011"; -- 0.423666
wait for 50 ns; sig_in <= "0010001010100010"; -- 0.270578
wait for 50 ns; sig_in <= "0000100001101101"; -- 0.065834
wait for 50 ns; sig_in <= "1110110010010100"; -- -0.151738
wait for 50 ns; sig_in <= "1101010001101000"; -- -0.340584
wait for 50 ns; sig_in <= "1100010010001111"; -- -0.464371
wait for 50 ns; sig_in <= "1100000000100000"; -- -0.499024
wait for 50 ns; sig_in <= "1100100000000000"; -- -0.437492
wait for 50 ns; sig_in <= "1101101010110111"; -- -0.291276
wait for 50 ns; sig_in <= "1111010010110000"; -- -0.088382
wait for 50 ns; sig_in <= "0001000011100100"; -- 0.131967
wait for 50 ns; sig_in <= "0010100111010111"; -- 0.326873
wait for 50 ns; sig_in <= "0011101010100100"; -- 0.458117
wait for 50 ns; sig_in <= "0011111111110110"; -- 0.499703
wait for 50 ns; sig_in <= "0011100010110111"; -- 0.443085
wait for 50 ns; sig_in <= "0010011001000111"; -- 0.299027
wait for 50 ns; sig_in <= "0000110000111110"; -- 0.095655
wait for 50 ns; sig_in <= "1110111111000000"; -- -0.126948
wait for 50 ns; sig_in <= "1101011001110011"; -- -0.324603
wait for 50 ns; sig_in <= "1100010101100111"; -- -0.457801
wait for 50 ns; sig_in <= "1100000000001011"; -- -0.499652
wait for 50 ns; sig_in <= "1100011110000000"; -- -0.441397
wait for 50 ns; sig_in <= "1101101001010011"; -- -0.294340
wait for 50 ns; sig_in <= "1111010011000100"; -- -0.087766
wait for 50 ns; sig_in <= "0001000110000011"; -- 0.136815
wait for 50 ns; sig_in <= "0010101010111111"; -- 0.333958
wait for 50 ns; sig_in <= "0011101101010100"; -- 0.463489
wait for 50 ns; sig_in <= "0011111111010111"; -- 0.498741
wait for 50 ns; sig_in <= "0011011101010000"; -- 0.432133
wait for 50 ns; sig_in <= "0010001101110010"; -- 0.276905
wait for 50 ns; sig_in <= "0000100001000101"; -- 0.064591
wait for 50 ns; sig_in <= "1110101101011011"; -- -0.161299
wait for 50 ns; sig_in <= "1101001010101011"; -- -0.354161
wait for 50 ns; sig_in <= "1100001101010111"; -- -0.473921
wait for 50 ns; sig_in <= "1100000010010110"; -- -0.495417
wait for 50 ns; sig_in <= "1100101100001001"; -- -0.413782
wait for 50 ns; sig_in <= "1110000010001110"; -- -0.245654
wait for 50 ns; sig_in <= "1111110010110000"; -- -0.025886
wait for 50 ns; sig_in <= "0001100110001100"; -- 0.199593
wait for 50 ns; sig_in <= "0011000100010010"; -- 0.383349
wait for 50 ns; sig_in <= "0011111001000100"; -- 0.486439
wait for 50 ns; sig_in <= "0011111001001101"; -- 0.486732
wait for 50 ns; sig_in <= "0011000100011111"; -- 0.383762
wait for 50 ns; sig_in <= "0001100101111010"; -- 0.199029
wait for 50 ns; sig_in <= "1111110001011110"; -- -0.028387
wait for 50 ns; sig_in <= "1101111111111111"; -- -0.250016
wait for 50 ns; sig_in <= "1100101001110101"; -- -0.418313
wait for 50 ns; sig_in <= "1100000001100110"; -- -0.496889
wait for 50 ns; sig_in <= "1100010000001010"; -- -0.468455
wait for 50 ns; sig_in <= "1101010010100100"; -- -0.338742
wait for 50 ns; sig_in <= "1110111010101001"; -- -0.135464
wait for 50 ns; sig_in <= "0000110001111011"; -- 0.097497
wait for 50 ns; sig_in <= "0010011110011110"; -- 0.309508
wait for 50 ns; sig_in <= "0011101000100011"; -- 0.454183
wait for 50 ns; sig_in <= "0011111111110010"; -- 0.499579
wait for 50 ns; sig_in <= "0011011110111001"; -- 0.435347
wait for 50 ns; sig_in <= "0010001100111010"; -- 0.275204
wait for 50 ns; sig_in <= "0000011011101110"; -- 0.054127
wait for 50 ns; sig_in <= "1110100100010000"; -- -0.179198
wait for 50 ns; sig_in <= "1101000001000000"; -- -0.373053
wait for 50 ns; sig_in <= "1100001000000111"; -- -0.484167
wait for 50 ns; sig_in <= "1100000110011011"; -- -0.487444
wait for 50 ns; sig_in <= "1100111100100011"; -- -0.381740
wait for 50 ns; sig_in <= "1110011110100011"; -- -0.190335
wait for 50 ns; sig_in <= "0000010110100100"; -- 0.044079
wait for 50 ns; sig_in <= "0010001001101010"; -- 0.268845
wait for 50 ns; sig_in <= "0011011101110001"; -- 0.433150
wait for 50 ns; sig_in <= "0011111111110001"; -- 0.499551
wait for 50 ns; sig_in <= "0011100111101111"; -- 0.452600
wait for 50 ns; sig_in <= "0010011010111010"; -- 0.302557
wait for 50 ns; sig_in <= "0000101010101001"; -- 0.083279
wait for 50 ns; sig_in <= "1110110000011111"; -- -0.155318
wait for 50 ns; sig_in <= "1101001000011010"; -- -0.358571
wait for 50 ns; sig_in <= "1100001010011101"; -- -0.479599
wait for 50 ns; sig_in <= "1100000101000010"; -- -0.490187
wait for 50 ns; sig_in <= "1100111001100111"; -- -0.387474
wait for 50 ns; sig_in <= "1110011100001111"; -- -0.194840
wait for 50 ns; sig_in <= "0000010110001011"; -- 0.043292
wait for 50 ns; sig_in <= "0010001011000101"; -- 0.271624
wait for 50 ns; sig_in <= "0011011111101001"; -- 0.436797
wait for 50 ns; sig_in <= "0011111111111101"; -- 0.499906
wait for 50 ns; sig_in <= "0011100100001111"; -- 0.445761
wait for 50 ns; sig_in <= "0010010010110001"; -- 0.286666
wait for 50 ns; sig_in <= "0000011110100110"; -- 0.059763
wait for 50 ns; sig_in <= "1110100011000011"; -- -0.181541
wait for 50 ns; sig_in <= "1100111101011001"; -- -0.380089
wait for 50 ns; sig_in <= "1100000101111000"; -- -0.488535
wait for 50 ns; sig_in <= "1100001001111000"; -- -0.480706
wait for 50 ns; sig_in <= "1101001000101100"; -- -0.358045
wait for 50 ns; sig_in <= "1110110011011101"; -- -0.149503
wait for 50 ns; sig_in <= "0000110000101111"; -- 0.095171
wait for 50 ns; sig_in <= "0010100010011011"; -- 0.317227
wait for 50 ns; sig_in <= "0011101101000100"; -- 0.463009
wait for 50 ns; sig_in <= "0011111110011101"; -- 0.496979
wait for 50 ns; sig_in <= "0011010010001011"; -- 0.410493
wait for 50 ns; sig_in <= "0001110010110000"; -- 0.224134
wait for 50 ns; sig_in <= "1111110111010001"; -- -0.017054
wait for 50 ns; sig_in <= "1101111101110001"; -- -0.254354
wait for 50 ns; sig_in <= "1100100100000001"; -- -0.429646
wait for 50 ns; sig_in <= "1100000000001011"; -- -0.499674
wait for 50 ns; sig_in <= "1100011011001110"; -- -0.446827
wait for 50 ns; sig_in <= "1101101110110000"; -- -0.283696
wait for 50 ns; sig_in <= "1111100110010010"; -- -0.050225
wait for 50 ns; sig_in <= "0001100100010101"; -- 0.195965
wait for 50 ns; sig_in <= "0011001001100110"; -- 0.393738
wait for 50 ns; sig_in <= "0011111100110000"; -- 0.493655
wait for 50 ns; sig_in <= "0011110000110110"; -- 0.470411
wait for 50 ns; sig_in <= "0010101000101001"; -- 0.329385
wait for 50 ns; sig_in <= "0000110110000010"; -- 0.105543
wait for 50 ns; sig_in <= "1110110101101101"; -- -0.145101
wait for 50 ns; sig_in <= "1101000111111110"; -- -0.359441
wait for 50 ns; sig_in <= "1100001000101000"; -- -0.483167
wait for 50 ns; sig_in <= "1100000111111000"; -- -0.484605
wait for 50 ns; sig_in <= "1101000110001011"; -- -0.362957
wait for 50 ns; sig_in <= "1110110011110101"; -- -0.148758
wait for 50 ns; sig_in <= "0000110101000100"; -- 0.103649
wait for 50 ns; sig_in <= "0010101000111000"; -- 0.329821
wait for 50 ns; sig_in <= "0011110001011111"; -- 0.471661
wait for 50 ns; sig_in <= "0011111100000111"; -- 0.492407
wait for 50 ns; sig_in <= "0011000101110010"; -- 0.386285
wait for 50 ns; sig_in <= "0001011100010011"; -- 0.180261
wait for 50 ns; sig_in <= "1111011010110011"; -- -0.072667
wait for 50 ns; sig_in <= "1101100010110100"; -- -0.307016
wait for 50 ns; sig_in <= "1100010011100101"; -- -0.461748
wait for 50 ns; sig_in <= "1100000001111100"; -- -0.496230
wait for 50 ns; sig_in <= "1100110010101011"; -- -0.401028
wait for 50 ns; sig_in <= "1110011001010010"; -- -0.200634
wait for 50 ns; sig_in <= "0000011010111110"; -- 0.052679
wait for 50 ns; sig_in <= "0010010101101101"; -- 0.292403
wait for 50 ns; sig_in <= "0011101001000101"; -- 0.455222
wait for 50 ns; sig_in <= "0011111110111000"; -- 0.497797
wait for 50 ns; sig_in <= "0011010001000111"; -- 0.408421
wait for 50 ns; sig_in <= "0001101011101110"; -- 0.210393
wait for 50 ns; sig_in <= "1111101001100001"; -- -0.043905
wait for 50 ns; sig_in <= "1101101101001100"; -- -0.286756
wait for 50 ns; sig_in <= "1100011000000000"; -- -0.453115
wait for 50 ns; sig_in <= "1100000000111111"; -- -0.498082
wait for 50 ns; sig_in <= "1100101110100001"; -- -0.409147
wait for 50 ns; sig_in <= "1110010100100101"; -- -0.209823
wait for 50 ns; sig_in <= "0000010111110001"; -- 0.046412
wait for 50 ns; sig_in <= "0010010100101010"; -- 0.290354
wait for 50 ns; sig_in <= "0011101001010110"; -- 0.455740
wait for 50 ns; sig_in <= "0011111110101000"; -- 0.497300
wait for 50 ns; sig_in <= "0011001110011111"; -- 0.403275
wait for 50 ns; sig_in <= "0001100101110110"; -- 0.198907
wait for 50 ns; sig_in <= "1111100001001100"; -- -0.060181
wait for 50 ns; sig_in <= "1101100100110111"; -- -0.303021
wait for 50 ns; sig_in <= "1100010011000110"; -- -0.462706
wait for 50 ns; sig_in <= "1100000010100111"; -- -0.494896
wait for 50 ns; sig_in <= "1100111000001100"; -- -0.390256
wait for 50 ns; sig_in <= "1110100101001101"; -- -0.177329
wait for 50 ns; sig_in <= "0000101011100100"; -- 0.085093
wait for 50 ns; sig_in <= "0010100101111100"; -- 0.324099
wait for 50 ns; sig_in <= "0011110010001000"; -- 0.472899
wait for 50 ns; sig_in <= "0011111010101010"; -- 0.489561
wait for 50 ns; sig_in <= "0010111100111010"; -- 0.368970
wait for 50 ns; sig_in <= "0001001010000001"; -- 0.144555
wait for 50 ns; sig_in <= "1111000010001001"; -- -0.120815
wait for 50 ns; sig_in <= "1101001011100110"; -- -0.352357
wait for 50 ns; sig_in <= "1100000111111110"; -- -0.484435
wait for 50 ns; sig_in <= "1100001010101000"; -- -0.479256
wait for 50 ns; sig_in <= "1101010011000010"; -- -0.337836
wait for 50 ns; sig_in <= "1111001100110011"; -- -0.100012
wait for 50 ns; sig_in <= "0001010101010100"; -- 0.166620
wait for 50 ns; sig_in <= "0011000101100011"; -- 0.385844
wait for 50 ns; sig_in <= "0011111101001111"; -- 0.494613
wait for 50 ns; sig_in <= "0011101100001100"; -- 0.461289
wait for 50 ns; sig_in <= "0010010111000011"; -- 0.295005
wait for 50 ns; sig_in <= "0000010110001100"; -- 0.043347
wait for 50 ns; sig_in <= "1110001110110010"; -- -0.221121
wait for 50 ns; sig_in <= "1100101000000101"; -- -0.421712
wait for 50 ns; sig_in <= "1100000000000100"; -- -0.499890
wait for 50 ns; sig_in <= "1100100010100101"; -- -0.432468
wait for 50 ns; sig_in <= "1110000101110100"; -- -0.238661
wait for 50 ns; sig_in <= "0000001100111010"; -- 0.025210
wait for 50 ns; sig_in <= "0010010000010111"; -- 0.281957
wait for 50 ns; sig_in <= "0011101001100000"; -- 0.456060
wait for 50 ns; sig_in <= "0011111101111011"; -- 0.495937
wait for 50 ns; sig_in <= "0011000111010111"; -- 0.389374
wait for 50 ns; sig_in <= "0001010101101111"; -- 0.167438
wait for 50 ns; sig_in <= "1111001010100011"; -- -0.104402
wait for 50 ns; sig_in <= "1101001111000111"; -- -0.345476
wait for 50 ns; sig_in <= "1100001000010001"; -- -0.483843
wait for 50 ns; sig_in <= "1100001011010110"; -- -0.477844
wait for 50 ns; sig_in <= "1101010111101010"; -- -0.328808
wait for 50 ns; sig_in <= "1111010110100010"; -- -0.080980
wait for 50 ns; sig_in <= "0001100010000001"; -- 0.191446
wait for 50 ns; sig_in <= "0011010000000111"; -- 0.406462
wait for 50 ns; sig_in <= "0011111111011110"; -- 0.498951
wait for 50 ns; sig_in <= "0011100001100011"; -- 0.440527
wait for 50 ns; sig_in <= "0001111111001100"; -- 0.248425
wait for 50 ns; sig_in <= "1111110110000101"; -- -0.019388
wait for 50 ns; sig_in <= "1101101111110110"; -- -0.281563
wait for 50 ns; sig_in <= "1100010101011111"; -- -0.458036
wait for 50 ns; sig_in <= "1100000010110011"; -- -0.494533
wait for 50 ns; sig_in <= "1100111101101111"; -- -0.379414
wait for 50 ns; sig_in <= "1110110100011100"; -- -0.147577
wait for 50 ns; sig_in <= "0001000010100010"; -- 0.129946
wait for 50 ns; sig_in <= "0010111100001111"; -- 0.367636
wait for 50 ns; sig_in <= "0011111011110101"; -- 0.491837
wait for 50 ns; sig_in <= "0011101101011010"; -- 0.463685
wait for 50 ns; sig_in <= "0010010101001110"; -- 0.291443
wait for 50 ns; sig_in <= "0000001110011111"; -- 0.028286
wait for 50 ns; sig_in <= "1110000011000110"; -- -0.243959
wait for 50 ns; sig_in <= "1100011110101000"; -- -0.440184
wait for 50 ns; sig_in <= "1100000000101100"; -- -0.498654
wait for 50 ns; sig_in <= "1100110010111010"; -- -0.400570
wait for 50 ns; sig_in <= "1110100101101111"; -- -0.176313
wait for 50 ns; sig_in <= "0000110101001001"; -- 0.103778
wait for 50 ns; sig_in <= "0010110011111001"; -- 0.351340
wait for 50 ns; sig_in <= "0011111001110010"; -- 0.487847
wait for 50 ns; sig_in <= "0011110000011100"; -- 0.469615
wait for 50 ns; sig_in <= "0010011010100111"; -- 0.301960
wait for 50 ns; sig_in <= "0000010011011001"; -- 0.037869
wait for 50 ns; sig_in <= "1110000101110110"; -- -0.238580
wait for 50 ns; sig_in <= "1100011111010010"; -- -0.438907
wait for 50 ns; sig_in <= "1100000000101110"; -- -0.498595
wait for 50 ns; sig_in <= "1100110100001110"; -- -0.398015
wait for 50 ns; sig_in <= "1110101001011100"; -- -0.169079
wait for 50 ns; sig_in <= "0000111010101110"; -- 0.114680
wait for 50 ns; sig_in <= "0010111001001001"; -- 0.361601
wait for 50 ns; sig_in <= "0011111011101001"; -- 0.491493
wait for 50 ns; sig_in <= "0011101100011100"; -- 0.461780
wait for 50 ns; sig_in <= "0010010000001101"; -- 0.281646
wait for 50 ns; sig_in <= "0000000100110101"; -- 0.009419
wait for 50 ns; sig_in <= "1101110111101111"; -- -0.266150
wait for 50 ns; sig_in <= "1100010111001011"; -- -0.454754
wait for 50 ns; sig_in <= "1100000010111111"; -- -0.494181
wait for 50 ns; sig_in <= "1101000010000011"; -- -0.370995
wait for 50 ns; sig_in <= "1110111111110101"; -- -0.125329
wait for 50 ns; sig_in <= "0001010010111100"; -- 0.161994
wait for 50 ns; sig_in <= "0011001010101110"; -- 0.395938
wait for 50 ns; sig_in <= "0011111111010101"; -- 0.498692
wait for 50 ns; sig_in <= "0011011111000100"; -- 0.435679
wait for 50 ns; sig_in <= "0001110100011011"; -- 0.227397
wait for 50 ns; sig_in <= "1111100010110011"; -- -0.057030
wait for 50 ns; sig_in <= "1101011010110100"; -- -0.322640
wait for 50 ns; sig_in <= "1100001010000110"; -- -0.480293
wait for 50 ns; sig_in <= "1100001011111100"; -- -0.476676
wait for 50 ns; sig_in <= "1101011111111111"; -- -0.312520
wait for 50 ns; sig_in <= "1111101010000111"; -- -0.042740
wait for 50 ns; sig_in <= "0001111011110010"; -- 0.241748
wait for 50 ns; sig_in <= "0011100011101000"; -- 0.444579
wait for 50 ns; sig_in <= "0011111110010010"; -- 0.496629
wait for 50 ns; sig_in <= "0011000010011011"; -- 0.379731
wait for 50 ns; sig_in <= "0001000100001110"; -- 0.133240
wait for 50 ns; sig_in <= "1110101110100110"; -- -0.159009
wait for 50 ns; sig_in <= "1100110100101100"; -- -0.397086
wait for 50 ns; sig_in <= "1100000000011100"; -- -0.499144
wait for 50 ns; sig_in <= "1100100100000000"; -- -0.429688
wait for 50 ns; sig_in <= "1110010011011001"; -- -0.212134
wait for 50 ns; sig_in <= "0000101000011000"; -- 0.078854
wait for 50 ns; sig_in <= "0010101111100010"; -- 0.342835
wait for 50 ns; sig_in <= "0011111001111110"; -- 0.488221
wait for 50 ns; sig_in <= "0011101101101010"; -- 0.464161
wait for 50 ns; sig_in <= "0010001110100111"; -- 0.278525
wait for 50 ns; sig_in <= "1111111101101111"; -- -0.004421
wait for 50 ns; sig_in <= "1101101101100010"; -- -0.286083
wait for 50 ns; sig_in <= "1100010000011110"; -- -0.467821
wait for 50 ns; sig_in <= "1100000111011001"; -- -0.485569
wait for 50 ns; sig_in <= "1101010101101101"; -- -0.332602
wait for 50 ns; sig_in <= "1111100000000110"; -- -0.062311
wait for 50 ns; sig_in <= "0001110101111000"; -- 0.230226
wait for 50 ns; sig_in <= "0011100010000110"; -- 0.441586
wait for 50 ns; sig_in <= "0011111110010001"; -- 0.496611
wait for 50 ns; sig_in <= "0011000000001010"; -- 0.375298
wait for 50 ns; sig_in <= "0000111101100110"; -- 0.120305
wait for 50 ns; sig_in <= "1110100100111101"; -- -0.177822
wait for 50 ns; sig_in <= "1100101100101101"; -- -0.412677
wait for 50 ns; sig_in <= "1100000000000001"; -- -0.499984
wait for 50 ns; sig_in <= "1100101111000111"; -- -0.407989
wait for 50 ns; sig_in <= "1110101001010110"; -- -0.169241
wait for 50 ns; sig_in <= "0001000010111010"; -- 0.130685
wait for 50 ns; sig_in <= "0011000100011110"; -- 0.383713
wait for 50 ns; sig_in <= "0011111111000101"; -- 0.498196
wait for 50 ns; sig_in <= "0011011101010100"; -- 0.432246
wait for 50 ns; sig_in <= "0001101011001010"; -- 0.209287
wait for 50 ns; sig_in <= "1111010001111010"; -- -0.090016
wait for 50 ns; sig_in <= "1101001001010101"; -- -0.356771
wait for 50 ns; sig_in <= "1100000011010111"; -- -0.493445
wait for 50 ns; sig_in <= "1100011001110010"; -- -0.449639
wait for 50 ns; sig_in <= "1110000100101010"; -- -0.240899
wait for 50 ns; sig_in <= "0000011100111101"; -- 0.056547
wait for 50 ns; sig_in <= "0010101010101110"; -- 0.333437
wait for 50 ns; sig_in <= "0011111001101001"; -- 0.487565
wait for 50 ns; sig_in <= "0011101100010110"; -- 0.461606
wait for 50 ns; sig_in <= "0010000111100000"; -- 0.264659
wait for 50 ns; sig_in <= "1111110000010011"; -- -0.030677
wait for 50 ns; sig_in <= "1101011110110010"; -- -0.314867
wait for 50 ns; sig_in <= "1100001001001110"; -- -0.482000
wait for 50 ns; sig_in <= "1100001111101100"; -- -0.469353
wait for 50 ns; sig_in <= "1101110000000100"; -- -0.281143
wait for 50 ns; sig_in <= "0000000110011101"; -- 0.012593
wait for 50 ns; sig_in <= "0010011010100011"; -- 0.301859
wait for 50 ns; sig_in <= "0011110100101001"; -- 0.477809
wait for 50 ns; sig_in <= "0011110010100101"; -- 0.473796
wait for 50 ns; sig_in <= "0010010100111010"; -- 0.290827
wait for 50 ns; sig_in <= "1111111110110011"; -- -0.002362
wait for 50 ns; sig_in <= "1101101001000000"; -- -0.294911
wait for 50 ns; sig_in <= "1100001100011101"; -- -0.475674
wait for 50 ns; sig_in <= "1100001100100010"; -- -0.475528
wait for 50 ns; sig_in <= "1101101001011110"; -- -0.294020
wait for 50 ns; sig_in <= "0000000000000000"; -- -0.000000
end process;
END;
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "half2_tb"
files = [
"../../../modules/filtdec/half2_tb.v",
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
vcd dumpfile half2_tb.vcd
vcd dumpvars -m half2_tb -l 1
run 100000 ns
exit
#!/bin/bash
hdlmake
make && make fuse TOP_MODULE=half2_tb && ./isim_proj -tclbatch isim_cmd
action = "simulation"
target = "altera"
sim_tool = "modelsim"
top_module = "half2_tb"
files = [
"../../../modules/filtdec/half2_tb.v",
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
#!/bin/bash
hdlmake
make
vsim -c -do vsim.do half2_tb
vcd file half2_tb.vcd;
vcd add -r /*;
run 100000ns;
quit;
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "tb_myfilter"
files = [
"../../../modules/fir/tb_myfilter.vhd",
"../../../modules/fir/myfilter.vhd"
]
vcd dumpfile tb_myfilter.vcd
vcd dumpvars -m tb_myfilter -l 1
run 100000 ns
exit
#!/bin/bash
hdlmake
make && make fuse TOP_MODULE=tb_myfilter && ./isim_proj -tclbatch isim_cmd
action = "simulation"
target = "altera"
sim_tool = "modelsim"
top_module = "tb_myfilter"
files = [
"../../../modules/fir/tb_myfilter.vhd",
"../../../modules/fir/myfilter.vhd"
]
#!/bin/bash
hdlmake
make
vsim -c -do vsim.do tb_myfilter
vcd file myfilter.vcd;
vcd add -r /*;
run 100000ns;
quit;
target = "altera"
action = "synthesis"
# Supported families on tools/quartus.py
# Quartus Web only supports the family ep2agx45:
syn_device = "ep2agx45cu"
syn_grade = "c6"
syn_package = "17"
syn_top = "half2"
syn_project = "half2"
#syn_tool = "quartus"
files = [
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
#!/bin/bash
hdlmake quartus-project
# Quartus bin needs to be exported to path
quartus_sh --tcl_eval load_package flow \; project_open half2 \; execute_flow -compile
#!/bin/bash
echo "set the appropriated HDLMAKE_RSYNTH variables in this file"
export HDLMAKE_RSYNTH_USER=javi
export HDLMAKE_RSYNTH_ISE_PATH="/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/"
export HDLMAKE_RSYNTH_SERVER="192.168.0.17"
hdlmake
make remote
make sync
make cleanremote
target = "altera"
action = "synthesis"
# Supported families on tools/quartus.py
# Quartus Web only supports the family ep2agx45:
syn_device = "ep2agx45cu"
syn_grade = "c6"
syn_package = "17"
syn_top = "myfilter"
syn_project = "myfilter"
#syn_tool = "quartus"
files = ["../../../modules/fir/myfilter.vhd"]
#!/bin/bash
hdlmake quartus-project
# Quartus bin needs to be exported to path
quartus_sh --tcl_eval load_package flow \; project_open myfilter \; execute_flow -compile
#!/bin/bash
echo "set the appropriated HDLMAKE_RSYNTH variables in this file"
export HDLMAKE_RSYNTH_USER=javi
export HDLMAKE_RSYNTH_ISE_PATH="/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin/"
export HDLMAKE_RSYNTH_SERVER="192.168.0.17"
hdlmake
make remote
make sync
make cleanremote
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "top_module"
files = [ "top_module_tb.vhd", "top_module.vhd" ]
#!/bin/bash
# Tests for empty parameter
if [ -z $1 ] ; then
echo "You must specify a top module testbench!";
echo "Usage: $0 <TOP_MODULE_WITHOUT_EXTENSION>";
exit 1;
fi
make && make fuse TOP_MODULE=$1 && ./isim_proj -view wave.wcfg -tclbatch isim_cmd -gui
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity top_module is
generic(
g_clk_period : natural := 100000000;
g_sim : boolean := true
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
function f_ceil_log2(x : natural) return natural is
begin
if x <= 1 then
return 0;
else
return f_ceil_log2((x+1)/2) + 1;
end if;
end f_ceil_log2;
-- Constant declaration
constant c_blink_num_pins : natural := 8;
constant c_counter_width : natural := f_ceil_log2(c_blink_num_pins);
constant c_counter_full : natural := c_blink_num_pins;
constant c_sim_clk_period : natural := 1;
constant c_clk_period : natural := g_clk_period;
-- Global clock
signal clk_sys : std_logic;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
signal s_counter_full : unsigned(c_counter_width-1 downto 0);
signal s_blink : std_logic_vector(c_blink_num_pins-1 downto 0);
signal rst_n : std_logic;
begin
clk_sys <= clk_i;
rst_n <= rst_n_i;
gen_sim_clk_period : if g_sim = true generate
s_counter_full <= to_unsigned(c_sim_clk_period, c_counter_width);
end generate;
gen_syn_clk_period : if g_sim = false generate
s_counter_full <= to_unsigned(c_clk_period, c_counter_width);
end generate;
p_counter : process (clk_sys)
begin
if rising_edge(clk_sys) then
if rst_n = '0' then
s_counter <= (others => '0');
s_blink <= x"01";
else
if (s_counter = s_counter_full-1) then
s_counter <= (others => '0');
s_blink <= s_blink(c_blink_num_pins-2 downto 0) & s_blink(c_blink_num_pins-1);
else
s_counter <= s_counter + 1;
end if;
end if;
end if;
end process;
blink_o <= s_blink;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_module_tb is -- entity declaration
end top_module_tb;
architecture sim of top_module_tb is
-- 100.00 MHz clock
constant c_clk_period : time := 10.00 ns;
constant c_rst_cycles : natural := 4;
constant c_sim_time : time := 1000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
signal clk100 : std_logic := '0';
signal s_locked : std_logic;
signal s_blink : std_logic_vector(7 downto 0);
signal s_rst_n : std_logic;
-- Components
component top_module
generic(
g_clk_period : natural := 100000000;
g_sim : boolean := true
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end component;
-- Functions
--function calculate_next_input_sample(sample_number : in integer) return std_logic_vector is
-- variable A : real := 1.0; -- Amplitude for wave
-- variable F : real := 100.0; -- Frequency for wave
-- variable P : real := 0.0; -- Phase for wave
-- variable theta : real;
-- variable y : real; -- The calculated value as a real
-- variable y_int : integer; -- The calculated value as an integer
-- variable result : std_logic_vector(c_ip_width-1 downto 0);
-- variable number_of_samples : real := 100.0 * real(47);
--begin
-- theta := (2.0 * MATH_PI * F * real(sample_number mod integer(number_of_samples))) / number_of_samples;
-- y := A * sin(theta + P);
-- y_int := integer(round(y * real(2**(c_ip_width-2))));
-- result := std_logic_vector(to_signed(y_int, c_ip_width));
-- return result;
--end function calculate_next_input_sample;
begin
cmp_top_module : top_module
generic map
(
g_clk_period => 4,
g_sim => false
)
port map
(
clk_i => clk100,
rst_n_i => s_rst_n,
blink_o => s_blink
);
p_clk_gen : process is
begin
while g_end_simulation = false loop
wait for c_clk_period/2;
clk100 <= not clk100;
wait for c_clk_period/2;
clk100 <= not clk100;
end loop;
wait; -- simulation stops here
end process p_clk_gen;
p_main_simulation : process is
begin
s_rst_n <= '0';
wait for c_rst_cycles*c_clk_period;
s_rst_n <= '1';
wait for 100*c_clk_period;
-- End simualtion
g_end_simulation <= true;
end process p_main_simulation;
end sim;
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="top_module_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="15" />
<wvobject fp_name="/top_module_tb/g_end_simulation" type="other" db_ref_id="1">
<obj_property name="ElementShortName">g_end_simulation</obj_property>
<obj_property name="ObjectShortName">g_end_simulation</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/clk100" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk100</obj_property>
<obj_property name="ObjectShortName">clk100</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/s_locked" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_locked</obj_property>
<obj_property name="ObjectShortName">s_locked</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/s_blink" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_blink[7:0]</obj_property>
<obj_property name="ObjectShortName">s_blink[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/c_clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_clk_period</obj_property>
<obj_property name="ObjectShortName">c_clk_period</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/c_sim_time" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_sim_time</obj_property>
<obj_property name="ObjectShortName">c_sim_time</obj_property>
</wvobject>
<wvobject fp_name="divider20" type="divider">
<obj_property name="label">cmp_top_module</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/blink_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">blink_o[7:0]</obj_property>
<obj_property name="ObjectShortName">blink_o[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/clk_sys" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_sys</obj_property>
<obj_property name="ObjectShortName">clk_sys</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/s_counter" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_counter[2:0]</obj_property>
<obj_property name="ObjectShortName">s_counter[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/s_blink" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_blink[7:0]</obj_property>
<obj_property name="ObjectShortName">s_blink[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/c_blink_num_pins" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_blink_num_pins</obj_property>
<obj_property name="ObjectShortName">c_blink_num_pins</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/c_counter_width" type="other" db_ref_id="1">
<obj_property name="ElementShortName">c_counter_width</obj_property>
<obj_property name="ObjectShortName">c_counter_width</obj_property>
</wvobject>
<wvobject fp_name="/top_module_tb/cmp_top_module/s_counter_full" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_counter_full[2:0]</obj_property>
<obj_property name="ObjectShortName">s_counter_full[2:0]</obj_property>
</wvobject>
</wave_config>
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