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Commit c97cff89 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Fix and upgrade the counter test demo HDL files

parent 1627ac83
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Showing with 39 additions and 33 deletions
tests/counter/modules/counter/verilog/counter.v
View file @ c97cff89
...@@ -20,28 +20,32 @@ module counter ( ...@@ -20,28 +20,32 @@ module counter (
input clock, clear, count; input clock, clear, count;
//--------- Internal Variables ------------------------ //--------- Internal Variables ------------------------
reg ready = 0;
reg [23:0] divider; reg [23:0] divider;
reg [7:0] Q; reg [7:0] Q;
//--------- Code Starts Here -------------------------- //--------- Code Starts Here --------------------------
always @(posedge clock) begin always @(posedge clock) begin
if (ready) if (clear)
begin begin
if (divider == cycles_per_second) Q <= 0;
begin divider <= 0;
divider <= 0;
Q <= {Q[6:0], Q[7]};
end
else
divider <= divider + 1;
end end
else else
begin begin
ready <= 1; if (count)
Q <= 8'b00010001; begin
divider <= 0; if (divider == cycles_per_second)
begin
divider <= 0;
Q <= Q + 1;
end
else
begin
divider <= divider + 1;
Q <= Q;
end
end
end end
end end
......
tests/counter/modules/counter/vhdl/counter.vhd
View file @ c97cff89
...@@ -24,7 +24,6 @@ end counter; ...@@ -24,7 +24,6 @@ end counter;
------------------------------------------------------- -------------------------------------------------------
architecture behv of counter is architecture behv of counter is
signal ready: std_logic;
signal Pre_Q: unsigned(7 downto 0); signal Pre_Q: unsigned(7 downto 0);
signal divider: unsigned(23 downto 0); signal divider: unsigned(23 downto 0);
...@@ -33,18 +32,19 @@ begin ...@@ -33,18 +32,19 @@ begin
process(clock, count, clear) process(clock, count, clear)
begin begin
if (clock='1' and clock'event) then if (clock='1' and clock'event) then
if ready = '1' then if clear = '1' then
if divider = cycles_per_second then Pre_Q <= (others => '0');
divider <= (others => '0');
Pre_Q(7 downto 1) <= Pre_Q(6 downto 0);
Pre_Q(0) <= Pre_Q(7);
else
divider <= divider + 1;
end if;
else
ready <= '1';
Pre_Q <= "00010001";
divider <= (others => '0'); divider <= (others => '0');
else
if count = '1' then
if divider = cycles_per_second then
divider <= (others => '0');
Pre_Q <= Pre_Q + 1;
else
divider <= divider + 1;
Pre_Q <= Pre_Q;
end if;
end if;
end if; end if;
end if; end if;
end process; end process;
......
tests/counter/testbench/counter_tb/verilog/counter_tb.v
View file @ c97cff89
...@@ -8,7 +8,7 @@ module counter_tb(); ...@@ -8,7 +8,7 @@ module counter_tb();
reg clock, clear, count; reg clock, clear, count;
wire [7:0] Q; wire [7:0] Q;
defparam U_counter.cycles_per_second = 500; defparam U_counter.cycles_per_second = 10;
// Initialize all variables // Initialize all variables
initial begin initial begin
...@@ -22,9 +22,8 @@ initial begin ...@@ -22,9 +22,8 @@ initial begin
count = 0; // initial value of count enable count = 0; // initial value of count enable
#5 clear = 1; // Assert the clear signal #5 clear = 1; // Assert the clear signal
#10 clear = 0; // De-assert clear signal #10 clear = 0; // De-assert clear signal
#10 count = 1; // Start count #40 count = 1; // Start count
#10000 count = 0; // De-assert count enable #1000 $finish; // Terminate simulation
#5 $finish; // Terminate simulation
end end
// Clock generator // Clock generator
......
tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd
View file @ c97cff89
...@@ -33,7 +33,7 @@ architecture testbench of counter_tb is ...@@ -33,7 +33,7 @@ architecture testbench of counter_tb is
begin begin
U_counter: counter U_counter: counter
generic map (cycles_per_second => 500) generic map (cycles_per_second => 10)
port map (t_clock, t_clear, t_count, t_Q); port map (t_clock, t_clear, t_count, t_Q);
process process
...@@ -47,12 +47,15 @@ begin ...@@ -47,12 +47,15 @@ begin
process process
begin begin
t_clear <= '1'; -- start counting t_clear <= '1'; -- clear counter
t_count <= '1'; t_count <= '0';
wait for 50 ns; wait for 50 ns;
t_clear <= '0'; -- clear output t_clear <= '0'; -- release clear
wait for 1000 ns; wait for 200 ns;
t_count <= '1';
wait for 1000 ns; -- start counting
report "Testbench of Adder completed successfully!" report "Testbench of Adder completed successfully!"
severity note; severity note;
......
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