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Hdlmake
Commit c2f8dff6 authored by Lucas Russo's avatar Lucas Russo Committed by Paweł Szostek
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various: small cleanup

parent 2d608ee0
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Showing with 51 additions and 53 deletions
src/__main__.py
View file @ c2f8dff6
......@@ -18,7 +18,7 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
# Modified to allow iSim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
import os
......@@ -37,8 +37,6 @@ def main():
parser.add_option("--manifest-help", action="store_true",
dest="manifest_help", help="print manifest file variables description")
# parser.add_option("--make-sim", dest="make_sim", action="store_true",
# default=None, help="generate a simulation Makefile")
parser.add_option("--make-vsim", dest="make_vsim", action="store_true",
default=None, help="generate a ModelSim simulation Makefile")
......
src/dep_solver.py
View file @ c2f8dff6
......@@ -17,6 +17,7 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
import msg as p
import global_mod
......
src/flow.py
View file @ c2f8dff6
......@@ -18,7 +18,8 @@
# along with this program if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
# Modified to allow iSim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br)
import xml.dom.minidom
......
src/global_mod.py
View file @ c2f8dff6
......@@ -18,6 +18,7 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
options = None
top_module = None
......
src/hdlmake_kernel.py
View file @ c2f8dff6
......@@ -18,7 +18,7 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
# Modified to allow iSim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
import os
import msg as p
......@@ -46,20 +46,31 @@ class HdlmakeKernel(object):
tm = self.top_module
if not self.modules_pool.is_everything_fetched():
self.fetch(unfetched_only = True)
self.fetch(unfetched_only=True)
if tm.action == "simulation":
if tm.use_compiler == "iverilog":
self.generate_iverilog_makefile()
elif tm.use_compiler == "isim" :
elif tm.use_compiler == "isim":
self.generate_isim_makefile()
elif tm.use_compiler == "vsim" or tm.use_compiler == "modelsim":
self.generate_vsim_makefile()
else:
raise RuntimeError("Unrecognized or not specified simulation tool: "+ str(tm.use_compiler))
quit()
# Force declaration of sim_tool varible in Manifest
#if tm.sim_tool == None:
# p.error("sim_tool variable must be defined in the manifest")
# quit()
## Make distintion between isim and vsim simulators
#if tm.sim_tool == "vsim":
# self.generate_modelsim_makefile()
#elif tm.sim_tool == "isim":
# self.generate_isim_makefile()
#else:
# raise RuntimeError("Unrecognized sim tool: "+tm.sim_tool)
elif tm.action == "synthesis":
if tm.syn_project == None:
if tm.syn_project is None:
p.error("syn_project variable must be defined in the manifest")
quit()
if tm.target.lower() == "xilinx":
......@@ -68,8 +79,8 @@ class HdlmakeKernel(object):
self.generate_remote_synthesis_makefile()
elif tm.target.lower() == "altera":
self.generate_quartus_project()
# self.generate_quartus_makefile()
# self.generate_quartus_remote_synthesis_makefile()
# self.generate_quartus_makefile()
# self.generate_quartus_remote_synthesis_makefile()
else:
raise RuntimeError("Unrecognized target: "+tm.target)
else:
......@@ -256,7 +267,7 @@ class HdlmakeKernel(object):
version_pattern = re.compile(".*?(\d\d\.\d).*") #First check if we have version in path
match = re.match(version_pattern, xst)
if match:
ise_version=match.group(1)
ise_version = match.group(1)
else: #If it is not the case call the "xst -h" to get version
xst_output = subprocess.Popen('xst -h', shell=True,
stdin=subprocess.PIPE, stdout=subprocess.PIPE, close_fds=True)
......@@ -266,7 +277,7 @@ class HdlmakeKernel(object):
re.compile('Release\s(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d)\s.*')
match = re.match(version_pattern, xst_output)
if match:
ise_version=''.join((match.group('major'), '.', match.group('minor')))
ise_version = ''.join((match.group('major'), '.', match.group('minor')))
else:
p.error("xst output is not in expected format: "+ xst_output +"\n"
"Can't determine ISE version")
......
src/makefile_writer.py
View file @ c2f8dff6
......@@ -18,7 +18,7 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
# Modified to allow iSim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
import os
import string
......@@ -119,8 +119,7 @@ endif
self.writeln(synthesis_cmd.format(ise_path, tcl))
self.writeln()
send_back_cmd = "__send_back: \n\t\tcd .. && rsync -e 'ssh -p $(PORT)' -avl $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)"
send_back_cmd = "__send_back: \n\t\tcd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)"
self.write(send_back_cmd)
self.write("\n\n")
......@@ -250,7 +249,6 @@ mrproper:
self.write("git checkout " + module.revision + ';')
self.write("cd $(PWD) \n\n")
<<<<<<< HEAD
def generate_iverilog_makefile(self, fileset, top_module, modules_pool):
from srcfile import VerilogFile, VHDLFile, SVFile
#open the file and write the above preambule (part 1)
......@@ -322,10 +320,7 @@ mrproper:
self.writeln("\t\trm -f "+" ".join(target_list)+"\n\t\trm -rf _xilinx")
def generate_modelsim_makefile(self, fileset, top_module):
=======
def generate_vsim_makefile(self, fileset, top_module):
>>>>>>> generate_modelsim_makefile call: fix name calling throughout the program
from srcfile import VerilogFile, VHDLFile, SVFile
from flow import ModelsiminiReader
make_preambule_p1 = """## variables #############################
......@@ -560,23 +555,14 @@ isim.wdb
# dependency meta-target. This rule just list the dependencies of the above file
#if len(vhdl.dep_depends_on) != 0:
#self.writeln(".PHONY: " + os.path.join(lib, purename, "."+purename))
# Touch the dependency file as well. In this way, "make" will recompile only what is needed (out of date)
# Touch the dependency file as well. In this way, "make" will recompile only what is needed (out of date)
self.write(os.path.join(lib, purename, "."+purename) +":")
for dep_file in vhdl.dep_depends_on:
name = dep_file.purename
self.write(" \\\n"+ os.path.join(dep_file.library, name, "."+name+ "_" + vhdl.extension()))
#self.write('\n\n')
self.write('\n')
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@\n")
# Fuse rule
#self.write("fuse:")
#self.write("ifeq ($(TOP_DESIGN),)")
#self.write("\t\techo \"Environment variable TOP_DESIGN not set!\"")
#self.write("else")
#self.write("\t\tfuse -intstyle ise -incremental")
#self.write(".PHONY: $(FUSE_PROJ)")
def __get_rid_of_incdirs(self, vlog_opt):
vlog_opt_vsim = self.__get_rid_of_vsim_incdirs(vlog_opt)
return self.__get_rid_of_isim_incdirs(vlog_opt_vsim)
......
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