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Hdlmake
Commits
c2f8dff6
Commit
c2f8dff6
authored
Nov 13, 2012
by
Lucas Russo
Committed by
Paweł Szostek
Jun 11, 2013
Browse files
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various: small cleanup
parent
2d608ee0
Hide whitespace changes
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Side-by-side
Showing
6 changed files
with
51 additions
and
53 deletions
+51
-53
__main__.py
src/__main__.py
+2
-4
dep_solver.py
src/dep_solver.py
+1
-0
flow.py
src/flow.py
+8
-7
global_mod.py
src/global_mod.py
+1
-0
hdlmake_kernel.py
src/hdlmake_kernel.py
+20
-9
makefile_writer.py
src/makefile_writer.py
+19
-33
No files found.
src/__main__.py
View file @
c2f8dff6
...
@@ -18,7 +18,7 @@
...
@@ -18,7 +18,7 @@
# along with this program; if not, write to the Free Software
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
#
# Modified to allow
i
Sim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow
I
Sim simulation by Lucas Russo (lucas.russo@lnls.br)
import
os
import
os
...
@@ -37,8 +37,6 @@ def main():
...
@@ -37,8 +37,6 @@ def main():
parser
.
add_option
(
"--manifest-help"
,
action
=
"store_true"
,
parser
.
add_option
(
"--manifest-help"
,
action
=
"store_true"
,
dest
=
"manifest_help"
,
help
=
"print manifest file variables description"
)
dest
=
"manifest_help"
,
help
=
"print manifest file variables description"
)
# parser.add_option("--make-sim", dest="make_sim", action="store_true",
# default=None, help="generate a simulation Makefile")
parser
.
add_option
(
"--make-vsim"
,
dest
=
"make_vsim"
,
action
=
"store_true"
,
parser
.
add_option
(
"--make-vsim"
,
dest
=
"make_vsim"
,
action
=
"store_true"
,
default
=
None
,
help
=
"generate a ModelSim simulation Makefile"
)
default
=
None
,
help
=
"generate a ModelSim simulation Makefile"
)
...
@@ -65,7 +63,7 @@ def main():
...
@@ -65,7 +63,7 @@ def main():
parser
.
add_option
(
"--list"
,
action
=
"store_true"
,
dest
=
"list"
,
parser
.
add_option
(
"--list"
,
action
=
"store_true"
,
dest
=
"list"
,
default
=
None
,
help
=
"List all modules together with their files"
)
default
=
None
,
help
=
"List all modules together with their files"
)
parser
.
add_option
(
"--list-files"
,
action
=
"store_true"
,
dest
=
"list_files"
,
parser
.
add_option
(
"--list-files"
,
action
=
"store_true"
,
dest
=
"list_files"
,
default
=
None
,
help
=
"List all files in a from of a space-separated string"
)
default
=
None
,
help
=
"List all files in a from of a space-separated string"
)
...
...
src/dep_solver.py
View file @
c2f8dff6
...
@@ -17,6 +17,7 @@
...
@@ -17,6 +17,7 @@
# along with this program; if not, write to the Free Software
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
#
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
import
msg
as
p
import
msg
as
p
import
global_mod
import
global_mod
...
...
src/flow.py
View file @
c2f8dff6
...
@@ -18,7 +18,8 @@
...
@@ -18,7 +18,8 @@
# along with this program if not, write to the Free Software
# along with this program if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
#
# Modified to allow iSim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br)
import
xml.dom.minidom
import
xml.dom.minidom
...
@@ -350,7 +351,7 @@ class XilinxsiminiReader(object):
...
@@ -350,7 +351,7 @@ class XilinxsiminiReader(object):
#p.info("Reading 'xilinxsim.ini' located in: '"+ str(self.path))
#p.info("Reading 'xilinxsim.ini' located in: '"+ str(self.path))
# Read loggical libraries name, skipping comments and other
# Read loggical libraries name, skipping comments and other
#possible sections
#possible sections
reading_libraries
=
False
reading_libraries
=
False
for
line
in
ini
:
for
line
in
ini
:
...
@@ -359,7 +360,7 @@ class XilinxsiminiReader(object):
...
@@ -359,7 +360,7 @@ class XilinxsiminiReader(object):
# Still in comments section
# Still in comments section
if
line
==
""
:
continue
if
line
==
""
:
continue
# Not in comments section. Library section:
# Not in comments section. Library section:
#<logical_library> = <phisical_path>
#<logical_library> = <phisical_path>
line
=
line
.
split
(
'='
)
line
=
line
.
split
(
'='
)
lib
=
line
[
0
]
.
strip
()
lib
=
line
[
0
]
.
strip
()
...
@@ -370,17 +371,17 @@ class XilinxsiminiReader(object):
...
@@ -370,17 +371,17 @@ class XilinxsiminiReader(object):
def
xilinxsim_ini_dir
():
def
xilinxsim_ini_dir
():
import
os
import
os
# Does not really need this
# Does not really need this
try
:
try
:
xilinx_path
=
os
.
environ
[
"XILINX"
]
xilinx_path
=
os
.
environ
[
"XILINX"
]
except
KeyError
:
except
KeyError
:
p
.
error
(
"Please set the environment variable XILINX"
)
p
.
error
(
"Please set the environment variable XILINX"
)
# Fail completely for now
# Fail completely for now
quit
()
quit
()
# Does not really need this
# Does not really need this
try
:
try
:
host_platform
=
os
.
environ
[
"HOST_PLATFORM"
]
host_platform
=
os
.
environ
[
"HOST_PLATFORM"
]
except
KeyError
:
except
KeyError
:
p
.
error
(
"Please set the environment variable HOST_PLATFORM"
)
p
.
error
(
"Please set the environment variable HOST_PLATFORM"
)
# Fail completely for now
# Fail completely for now
quit
()
quit
()
...
...
src/global_mod.py
View file @
c2f8dff6
...
@@ -18,6 +18,7 @@
...
@@ -18,6 +18,7 @@
# along with this program; if not, write to the Free Software
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
#
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
options
=
None
options
=
None
top_module
=
None
top_module
=
None
...
...
src/hdlmake_kernel.py
View file @
c2f8dff6
...
@@ -18,7 +18,7 @@
...
@@ -18,7 +18,7 @@
# along with this program; if not, write to the Free Software
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
#
# Modified to allow
i
Sim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow
I
Sim simulation by Lucas Russo (lucas.russo@lnls.br)
import
os
import
os
import
msg
as
p
import
msg
as
p
...
@@ -46,20 +46,31 @@ class HdlmakeKernel(object):
...
@@ -46,20 +46,31 @@ class HdlmakeKernel(object):
tm
=
self
.
top_module
tm
=
self
.
top_module
if
not
self
.
modules_pool
.
is_everything_fetched
():
if
not
self
.
modules_pool
.
is_everything_fetched
():
self
.
fetch
(
unfetched_only
=
True
)
self
.
fetch
(
unfetched_only
=
True
)
if
tm
.
action
==
"simulation"
:
if
tm
.
action
==
"simulation"
:
if
tm
.
use_compiler
==
"iverilog"
:
if
tm
.
use_compiler
==
"iverilog"
:
self
.
generate_iverilog_makefile
()
self
.
generate_iverilog_makefile
()
elif
tm
.
use_compiler
==
"isim"
:
elif
tm
.
use_compiler
==
"isim"
:
self
.
generate_isim_makefile
()
self
.
generate_isim_makefile
()
elif
tm
.
use_compiler
==
"vsim"
or
tm
.
use_compiler
==
"modelsim"
:
elif
tm
.
use_compiler
==
"vsim"
or
tm
.
use_compiler
==
"modelsim"
:
self
.
generate_vsim_makefile
()
self
.
generate_vsim_makefile
()
else
:
else
:
raise
RuntimeError
(
"Unrecognized or not specified simulation tool: "
+
str
(
tm
.
use_compiler
))
raise
RuntimeError
(
"Unrecognized or not specified simulation tool: "
+
str
(
tm
.
use_compiler
))
quit
()
quit
()
# Force declaration of sim_tool varible in Manifest
#if tm.sim_tool == None:
# p.error("sim_tool variable must be defined in the manifest")
# quit()
## Make distintion between isim and vsim simulators
#if tm.sim_tool == "vsim":
# self.generate_modelsim_makefile()
#elif tm.sim_tool == "isim":
# self.generate_isim_makefile()
#else:
# raise RuntimeError("Unrecognized sim tool: "+tm.sim_tool)
elif
tm
.
action
==
"synthesis"
:
elif
tm
.
action
==
"synthesis"
:
if
tm
.
syn_project
==
None
:
if
tm
.
syn_project
is
None
:
p
.
error
(
"syn_project variable must be defined in the manifest"
)
p
.
error
(
"syn_project variable must be defined in the manifest"
)
quit
()
quit
()
if
tm
.
target
.
lower
()
==
"xilinx"
:
if
tm
.
target
.
lower
()
==
"xilinx"
:
...
@@ -67,9 +78,9 @@ class HdlmakeKernel(object):
...
@@ -67,9 +78,9 @@ class HdlmakeKernel(object):
self
.
generate_ise_makefile
()
self
.
generate_ise_makefile
()
self
.
generate_remote_synthesis_makefile
()
self
.
generate_remote_synthesis_makefile
()
elif
tm
.
target
.
lower
()
==
"altera"
:
elif
tm
.
target
.
lower
()
==
"altera"
:
self
.
generate_quartus_project
()
self
.
generate_quartus_project
()
#
self.generate_quartus_makefile()
#
self.generate_quartus_makefile()
#
self.generate_quartus_remote_synthesis_makefile()
#
self.generate_quartus_remote_synthesis_makefile()
else
:
else
:
raise
RuntimeError
(
"Unrecognized target: "
+
tm
.
target
)
raise
RuntimeError
(
"Unrecognized target: "
+
tm
.
target
)
else
:
else
:
...
@@ -256,7 +267,7 @@ class HdlmakeKernel(object):
...
@@ -256,7 +267,7 @@ class HdlmakeKernel(object):
version_pattern
=
re
.
compile
(
".*?(
\
d
\
d
\
.
\
d).*"
)
#First check if we have version in path
version_pattern
=
re
.
compile
(
".*?(
\
d
\
d
\
.
\
d).*"
)
#First check if we have version in path
match
=
re
.
match
(
version_pattern
,
xst
)
match
=
re
.
match
(
version_pattern
,
xst
)
if
match
:
if
match
:
ise_version
=
match
.
group
(
1
)
ise_version
=
match
.
group
(
1
)
else
:
#If it is not the case call the "xst -h" to get version
else
:
#If it is not the case call the "xst -h" to get version
xst_output
=
subprocess
.
Popen
(
'xst -h'
,
shell
=
True
,
xst_output
=
subprocess
.
Popen
(
'xst -h'
,
shell
=
True
,
stdin
=
subprocess
.
PIPE
,
stdout
=
subprocess
.
PIPE
,
close_fds
=
True
)
stdin
=
subprocess
.
PIPE
,
stdout
=
subprocess
.
PIPE
,
close_fds
=
True
)
...
@@ -266,7 +277,7 @@ class HdlmakeKernel(object):
...
@@ -266,7 +277,7 @@ class HdlmakeKernel(object):
re
.
compile
(
'Release
\
s(?P<major>
\
d|
\
d
\
d)[^
\
d](?P<minor>
\
d|
\
d
\
d)
\
s.*'
)
re
.
compile
(
'Release
\
s(?P<major>
\
d|
\
d
\
d)[^
\
d](?P<minor>
\
d|
\
d
\
d)
\
s.*'
)
match
=
re
.
match
(
version_pattern
,
xst_output
)
match
=
re
.
match
(
version_pattern
,
xst_output
)
if
match
:
if
match
:
ise_version
=
''
.
join
((
match
.
group
(
'major'
),
'.'
,
match
.
group
(
'minor'
)))
ise_version
=
''
.
join
((
match
.
group
(
'major'
),
'.'
,
match
.
group
(
'minor'
)))
else
:
else
:
p
.
error
(
"xst output is not in expected format: "
+
xst_output
+
"
\n
"
p
.
error
(
"xst output is not in expected format: "
+
xst_output
+
"
\n
"
"Can't determine ISE version"
)
"Can't determine ISE version"
)
...
...
src/makefile_writer.py
View file @
c2f8dff6
...
@@ -18,7 +18,7 @@
...
@@ -18,7 +18,7 @@
# along with this program; if not, write to the Free Software
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
#
# Modified to allow
i
Sim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow
I
Sim simulation by Lucas Russo (lucas.russo@lnls.br)
import
os
import
os
import
string
import
string
...
@@ -59,7 +59,7 @@ class MakefileWriter(object):
...
@@ -59,7 +59,7 @@ class MakefileWriter(object):
self
.
_file
=
open
(
filename
,
"w"
)
self
.
_file
=
open
(
filename
,
"w"
)
def
generate_remote_synthesis_makefile
(
self
,
files
,
name
,
cwd
,
user
,
server
,
ise_path
):
def
generate_remote_synthesis_makefile
(
self
,
files
,
name
,
cwd
,
user
,
server
,
ise_path
):
import
path
import
path
if
name
==
None
:
if
name
==
None
:
import
random
import
random
name
=
''
.
join
(
random
.
choice
(
string
.
ascii_letters
+
string
.
digits
)
for
x
in
range
(
8
))
name
=
''
.
join
(
random
.
choice
(
string
.
ascii_letters
+
string
.
digits
)
for
x
in
range
(
8
))
...
@@ -82,12 +82,12 @@ endif
...
@@ -82,12 +82,12 @@ endif
else
:
else
:
user_tmpl
=
user_tmpl
.
format
(
user
)
user_tmpl
=
user_tmpl
.
format
(
user
)
test_tmpl
=
"__test_for_remote_synthesis_variables:
\n\t\t
true #dummy
\n
"
test_tmpl
=
"__test_for_remote_synthesis_variables:
\n\t\t
true #dummy
\n
"
if
server
==
None
:
if
server
==
None
:
server_tmpl
=
server_tmpl
.
format
(
"$(HDLMAKE_SERVER)#take the value from the environment"
)
server_tmpl
=
server_tmpl
.
format
(
"$(HDLMAKE_SERVER)#take the value from the environment"
)
else
:
else
:
server_tmpl
=
server_tmpl
.
format
(
server
)
server_tmpl
=
server_tmpl
.
format
(
server
)
remote_name_tmpl
=
remote_name_tmpl
.
format
(
name
)
remote_name_tmpl
=
remote_name_tmpl
.
format
(
name
)
self
.
initialize
()
self
.
initialize
()
self
.
writeln
(
user_tmpl
)
self
.
writeln
(
user_tmpl
)
...
@@ -119,8 +119,7 @@ endif
...
@@ -119,8 +119,7 @@ endif
self
.
writeln
(
synthesis_cmd
.
format
(
ise_path
,
tcl
))
self
.
writeln
(
synthesis_cmd
.
format
(
ise_path
,
tcl
))
self
.
writeln
()
self
.
writeln
()
send_back_cmd
=
"__send_back:
\n\t\t
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)"
send_back_cmd
=
"__send_back:
\n\t\t
cd .. && rsync -e 'ssh -p $(PORT)' -avl $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)"
self
.
write
(
send_back_cmd
)
self
.
write
(
send_back_cmd
)
self
.
write
(
"
\n\n
"
)
self
.
write
(
"
\n\n
"
)
...
@@ -133,7 +132,7 @@ endif
...
@@ -133,7 +132,7 @@ endif
pass
pass
def
generate_ise_makefile
(
self
,
top_mod
,
ise_path
):
def
generate_ise_makefile
(
self
,
top_mod
,
ise_path
):
import
path
import
path
mk_text
=
"""PROJECT := {1}
mk_text
=
"""PROJECT := {1}
ISE_CRAP :=
\
ISE_CRAP :=
\
*.b
\
*.b
\
...
@@ -193,7 +192,7 @@ local:
...
@@ -193,7 +192,7 @@ local:
clean:
clean:
\t\t
rm -f $(ISE_CRAP)
\t\t
rm -f $(ISE_CRAP)
\t\t
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
\t\t
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
#target for cleaning final files
mrproper:
mrproper:
\t\t
rm -f *.bit *.bin *.mcs
\t\t
rm -f *.bit *.bin *.mcs
...
@@ -250,7 +249,6 @@ mrproper:
...
@@ -250,7 +249,6 @@ mrproper:
self
.
write
(
"git checkout "
+
module
.
revision
+
';'
)
self
.
write
(
"git checkout "
+
module
.
revision
+
';'
)
self
.
write
(
"cd $(PWD)
\n\n
"
)
self
.
write
(
"cd $(PWD)
\n\n
"
)
<<<<<<<
HEAD
def
generate_iverilog_makefile
(
self
,
fileset
,
top_module
,
modules_pool
):
def
generate_iverilog_makefile
(
self
,
fileset
,
top_module
,
modules_pool
):
from
srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
from
srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
#open the file and write the above preambule (part 1)
#open the file and write the above preambule (part 1)
...
@@ -322,10 +320,7 @@ mrproper:
...
@@ -322,10 +320,7 @@ mrproper:
self
.
writeln
(
"
\t\t
rm -f "
+
" "
.
join
(
target_list
)
+
"
\n\t\t
rm -rf _xilinx"
)
self
.
writeln
(
"
\t\t
rm -f "
+
" "
.
join
(
target_list
)
+
"
\n\t\t
rm -rf _xilinx"
)
def
generate_modelsim_makefile
(
self
,
fileset
,
top_module
):
=======
def
generate_vsim_makefile
(
self
,
fileset
,
top_module
):
def
generate_vsim_makefile
(
self
,
fileset
,
top_module
):
>>>>>>>
generate_modelsim_makefile
call
:
fix
name
calling
throughout
the
program
from
srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
from
srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
from
flow
import
ModelsiminiReader
from
flow
import
ModelsiminiReader
make_preambule_p1
=
"""## variables #############################
make_preambule_p1
=
"""## variables #############################
...
@@ -336,10 +331,10 @@ MODELSIM_INI_PATH := """ + ModelsiminiReader.modelsim_ini_dir() + """
...
@@ -336,10 +331,10 @@ MODELSIM_INI_PATH := """ + ModelsiminiReader.modelsim_ini_dir() + """
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini """
+
self
.
__get_rid_of_incdirs
(
top_module
.
vlog_opt
)
+
"""
VLOG_FLAGS := -quiet -modelsimini modelsim.ini """
+
self
.
__get_rid_of_incdirs
(
top_module
.
vlog_opt
)
+
"""
"""
"""
make_preambule_p2
=
"""## rules #################################
make_preambule_p2
=
"""## rules #################################
sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
...
@@ -393,7 +388,7 @@ clean:
...
@@ -393,7 +388,7 @@ clean:
for
lib
in
libs
:
for
lib
in
libs
:
self
.
write
(
lib
+
"/."
+
lib
+
":
\n
"
)
self
.
write
(
lib
+
"/."
+
lib
+
":
\n
"
)
self
.
write
(
' '
.
join
([
"
\t
(vlib"
,
lib
,
"&&"
,
"vmap"
,
"-modelsimini modelsim.ini"
,
self
.
write
(
' '
.
join
([
"
\t
(vlib"
,
lib
,
"&&"
,
"vmap"
,
"-modelsimini modelsim.ini"
,
lib
,
"&&"
,
"touch"
,
lib
+
"/."
+
lib
,
")"
]))
lib
,
"&&"
,
"touch"
,
lib
+
"/."
+
lib
,
")"
]))
self
.
write
(
' '
.
join
([
"||"
,
"rm -rf"
,
lib
,
"
\n
"
]))
self
.
write
(
' '
.
join
([
"||"
,
"rm -rf"
,
lib
,
"
\n
"
]))
...
@@ -420,7 +415,7 @@ clean:
...
@@ -420,7 +415,7 @@ clean:
#list rules for all _primary.dat files for vhdl
#list rules for all _primary.dat files for vhdl
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
lib
=
vhdl
.
library
lib
=
vhdl
.
library
purename
=
vhdl
.
purename
purename
=
vhdl
.
purename
#each .dat depends on corresponding .vhd file
#each .dat depends on corresponding .vhd file
self
.
write
(
os
.
path
.
join
(
lib
,
purename
,
"."
+
purename
+
"_"
+
vhdl
.
extension
())
+
": "
+
vhdl
.
rel_path
())
self
.
write
(
os
.
path
.
join
(
lib
,
purename
,
"."
+
purename
+
"_"
+
vhdl
.
extension
())
+
": "
+
vhdl
.
rel_path
())
for
dep_file
in
vhdl
.
dep_depends_on
:
for
dep_file
in
vhdl
.
dep_depends_on
:
...
@@ -437,7 +432,7 @@ clean:
...
@@ -437,7 +432,7 @@ clean:
from
flow
import
XilinxsiminiReader
from
flow
import
XilinxsiminiReader
make_preambule_p1
=
"""## variables #############################
make_preambule_p1
=
"""## variables #############################
PWD := $(shell pwd)
PWD := $(shell pwd)
TOP_MODULE :=
TOP_MODULE :=
FUSE_OUTPUT ?= isim_proj
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := """
+
XilinxsiminiReader
.
xilinxsim_ini_dir
()
+
"""
XILINX_INI_PATH := """
+
XilinxsiminiReader
.
xilinxsim_ini_dir
()
+
"""
...
@@ -445,10 +440,10 @@ XILINX_INI_PATH := """ + XilinxsiminiReader.xilinxsim_ini_dir() + """
...
@@ -445,10 +440,10 @@ XILINX_INI_PATH := """ + XilinxsiminiReader.xilinxsim_ini_dir() + """
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """
+
self
.
__get_rid_of_incdirs
(
top_module
.
vlog_opt
)
+
"""
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """
+
self
.
__get_rid_of_incdirs
(
top_module
.
vlog_opt
)
+
"""
"""
"""
make_preambule_p2
=
"""## rules #################################
make_preambule_p2
=
"""## rules #################################
sim: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
sim: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
...
@@ -461,7 +456,7 @@ else
...
@@ -461,7 +456,7 @@ else
endif
endif
clean:
clean:
\t\t
rm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log
\
\t\t
rm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log
\
isim.wdb
isim.wdb
.PHONY: clean
.PHONY: clean
"""
"""
...
@@ -507,8 +502,8 @@ isim.wdb
...
@@ -507,8 +502,8 @@ isim.wdb
self
.
write
(
'
\n
'
)
self
.
write
(
'
\n
'
)
self
.
write
(
make_preambule_p2
)
self
.
write
(
make_preambule_p2
)
# ISim does not have a vmap command to insert additional libraries in
# ISim does not have a vmap command to insert additional libraries in
#.ini file.
#.ini file.
for
lib
in
libs
:
for
lib
in
libs
:
self
.
write
(
lib
+
"/."
+
lib
+
":
\n
"
)
self
.
write
(
lib
+
"/."
+
lib
+
":
\n
"
)
self
.
write
(
' '
.
join
([
"
\t
(mkdir"
,
lib
,
"&&"
,
"touch"
,
lib
+
"/."
+
lib
+
" "
]))
self
.
write
(
' '
.
join
([
"
\t
(mkdir"
,
lib
,
"&&"
,
"touch"
,
lib
+
"/."
+
lib
+
" "
]))
...
@@ -547,7 +542,7 @@ isim.wdb
...
@@ -547,7 +542,7 @@ isim.wdb
#list rules for all _primary.dat files for vhdl
#list rules for all _primary.dat files for vhdl
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
lib
=
vhdl
.
library
lib
=
vhdl
.
library
purename
=
vhdl
.
purename
purename
=
vhdl
.
purename
comp_obj
=
os
.
path
.
join
(
lib
,
purename
)
comp_obj
=
os
.
path
.
join
(
lib
,
purename
)
objs
.
append
(
comp_obj
)
objs
.
append
(
comp_obj
)
#each .dat depends on corresponding .vhd file and its dependencies
#each .dat depends on corresponding .vhd file and its dependencies
...
@@ -560,23 +555,14 @@ isim.wdb
...
@@ -560,23 +555,14 @@ isim.wdb
# dependency meta-target. This rule just list the dependencies of the above file
# dependency meta-target. This rule just list the dependencies of the above file
#if len(vhdl.dep_depends_on) != 0:
#if len(vhdl.dep_depends_on) != 0:
#self.writeln(".PHONY: " + os.path.join(lib, purename, "."+purename))
#self.writeln(".PHONY: " + os.path.join(lib, purename, "."+purename))
# Touch the dependency file as well. In this way, "make" will recompile only what is needed (out of date)
# Touch the dependency file as well. In this way, "make" will recompile only what is needed (out of date)
self
.
write
(
os
.
path
.
join
(
lib
,
purename
,
"."
+
purename
)
+
":"
)
self
.
write
(
os
.
path
.
join
(
lib
,
purename
,
"."
+
purename
)
+
":"
)
for
dep_file
in
vhdl
.
dep_depends_on
:
for
dep_file
in
vhdl
.
dep_depends_on
:
name
=
dep_file
.
purename
name
=
dep_file
.
purename
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
dep_file
.
library
,
name
,
"."
+
name
+
"_"
+
vhdl
.
extension
()))
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
dep_file
.
library
,
name
,
"."
+
name
+
"_"
+
vhdl
.
extension
()))
#self.write('\n\n')
self
.
write
(
'
\n
'
)
self
.
write
(
'
\n
'
)
self
.
writeln
(
"
\t\t
@mkdir -p $(dir $@) && touch $@
\n
"
)
self
.
writeln
(
"
\t\t
@mkdir -p $(dir $@) && touch $@
\n
"
)
# Fuse rule
#self.write("fuse:")
#self.write("ifeq ($(TOP_DESIGN),)")
#self.write("\t\techo \"Environment variable TOP_DESIGN not set!\"")
#self.write("else")
#self.write("\t\tfuse -intstyle ise -incremental")
#self.write(".PHONY: $(FUSE_PROJ)")
def
__get_rid_of_incdirs
(
self
,
vlog_opt
):
def
__get_rid_of_incdirs
(
self
,
vlog_opt
):
vlog_opt_vsim
=
self
.
__get_rid_of_vsim_incdirs
(
vlog_opt
)
vlog_opt_vsim
=
self
.
__get_rid_of_vsim_incdirs
(
vlog_opt
)
return
self
.
__get_rid_of_isim_incdirs
(
vlog_opt_vsim
)
return
self
.
__get_rid_of_isim_incdirs
(
vlog_opt_vsim
)
...
...
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