Merge cores is temporarly suppressed

parent 84ea22e5
......@@ -124,8 +124,6 @@ def _action_runner(modules_pool):
modules_pool.list_modules()
elif options.command == "list-files":
modules_pool.list_files()
elif options.command == "merge-cores":
modules_pool.merge_cores()
elif options.command == "tree":
modules_pool.generate_tree()
......
......@@ -192,61 +192,3 @@ class ActionCore(Action):
self._print_file_list(mod_aux.files)
self._print_comment("# MODULE END -> %s" % mod_aux.url)
self._print_comment("")
def merge_cores(self):
"""Merge the design into a single VHDL and a single Verilog file"""
self.check_all_fetched_or_quit()
logging.info("Merging all cores into one source file per language.")
flist = self.build_file_set()
base = self.options.dest
file_header = (
"\n\n\n\n"
"------------------------ WARNING --------------------------\n"
"-- This code has been generated by hdlmake merge-cores --\n"
"-- Please DO NOT MODIFY this file. If you need to change --\n"
"-- something inside, edit the original source file and --\n"
"-- re-generate the merged version! --\n"
"-----------------------------------------------------------\n"
"\n\n\n\n"
)
# Generate a VHDL file containing all the required VHDL files
f_out = open(base + ".vhd", "w")
f_out.write(file_header)
for vhdl in flist.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n" % vhdl.rel_path())
f_out.write("--- Source: %s\n" % vhdl.module.url)
if vhdl.module.revision:
f_out.write("--- Revision: %s\n" % vhdl.module.revision)
f_out.write("--- Last modified: %s\n" %
time.ctime(os.path.getmtime(vhdl.path)))
f_out.write(open(vhdl.rel_path(), "r").read() + "\n\n")
# print("VHDL: %s" % vhdl.rel_path())
f_out.close()
# Generate a VHDL file containing all the required VHDL files
f_out = open(base + ".v", "w")
f_out.write(file_header)
for vlog in flist.filter(VerilogFile):
f_out.write("\n\n// File: %s\n" % vlog.rel_path())
f_out.write("// Source: %s\n" % vlog.module.url)
if vlog.module.revision:
f_out.write("// Revision: %s\n" % vlog.module.revision)
f_out.write("// Last modified: %s\n" %
time.ctime(os.path.getmtime(vlog.path)))
vpp = VerilogPreprocessor()
for include_path in vlog.include_dirs:
vpp.add_path(include_path)
vpp.add_path(vlog.dirname)
f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close()
# Handling NGC files
current_path = os.getcwd()
for ngc in flist.filter(NGCFile):
import shutil
logging.info("copying NGC file: %s", ngc.rel_path())
shutil.copy(ngc.rel_path(), current_path)
logging.info("Cores merged.")
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