Refactoring in progress: no global variables

parent b2ff69ad
......@@ -28,7 +28,6 @@ import argparse
import logging
import sys
from . import global_mod
from .util.termcolor import colored
from .manifest_parser import ManifestParser
from .module_pool import ModulePool
......@@ -49,9 +48,6 @@ def main():
-- prepare the global module containing the heavy common stuff
"""
# Remember current path
global_mod.current_path = os.getcwd()
#
# SET & GET PARSER
#
......@@ -61,12 +57,7 @@ def main():
# PARSE & GET OPTIONS
#
options = _get_options(sys, parser)
global_mod.options = options
# global_mod_assigned!!!
env = Env(options)
global_mod.env = env
# Here we set the log level (A.K.A.) debug verbosity)
numeric_level = getattr(logging, options.log.upper(), None)
......@@ -79,15 +70,20 @@ def main():
# Create a ModulePool object, this will become our workspace
modules_pool = ModulePool()
# Set the environment
env = Env(options)
modules_pool.set_environment(env)
# Now, we add the first module, the one from which we are launching the program:
# Note that we are asking for not processing the manifest and specifying
# that there is not a parent module.
# 1- Hdlmake create a new Module() object
# 2- There is not a top_module yet in modules_pool, so only this time...:
# - this becomes the top_module (for both modules_pool and global_mod)
# - this becomes the top_module
# - the manifest is parsed & processed
current_path = os.getcwd()
modules_pool.new_module(parent=None,
url=global_mod.current_path,
url=current_path,
source=fetch_mod.LOCAL,
fetchto=".")
......@@ -102,37 +98,6 @@ def main():
# Setting global variables for top_module and mod_pool:
# -- Note that this is redundant, we can get top_mod from mod_pool!
top_mod = modules_pool.get_top_module()
global_mod.mod_pool = modules_pool
global_mod.top_module = top_mod
#
# Load global tool object (global_mod.py)
#
if top_mod.action == "synthesis":
if not top_mod.syn_tool:
logging.error("`syn_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to synthesize the project")
quit()
tool_name = top_mod.syn_tool
elif top_mod.action == "simulation":
if not top_mod.sim_tool:
logging.error("`sim_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to simulate the project")
quit()
tool_name = top_mod.sim_tool
else:
tool_name = "notool"
logging.info('import tool module: ' + tool_name)
try:
tool_module = importlib.import_module("hdlmake.tools.%s.%s" % (tool_name, tool_name))
except Exception as e:
logging.error(e)
quit()
global_mod.tool_module = tool_module
# #
# DECODE THE COMMANDS/ACTIONS HERE #
......@@ -287,9 +252,6 @@ def _get_parser():
parser.add_argument("--generate-project-vhd", help="generate project.vhd file with a meta package describing the project",
dest="generate_project_vhd", default=False, action="store_true")
parser.add_argument("--force", help="force hdlmake to generate the makefile, even if the specified tool is missing", default=False, action="store_true")
parser.add_argument("--no-parse", dest="no_parse",
default=False, help="disable smart parser engine", action="store_true")
return parser
......
......@@ -34,9 +34,3 @@ class CheckManifest(Action):
### THIS IS JUST A STUB
###
pass
#manifest_parser = ManifestParser()
#manifest_parser.add_arbitrary_code("__manifest=\""+self.path+"\"")
#manifest_parser.add_arbitrary_code(global_mod.options.arbitrary_code)
#opt_map = manifest_parser.parse()
......@@ -21,7 +21,6 @@
import logging
from hdlmake import global_mod
from hdlmake.makefile_writer import MakefileWriter
from .action import Action
......
......@@ -31,8 +31,6 @@ from hdlmake.vlog_parser import VerilogPreprocessor
from .action import Action
from hdlmake import global_mod
class MergeCores(Action):
def _check_manifest(self):
......@@ -99,9 +97,10 @@ class MergeCores(Action):
f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close()
current_path = os.getcwd()
for ngc in flist.filter(NGCFile):
import shutil
logging.info("copying NGC file: %s" % ngc.rel_path())
shutil.copy(ngc.rel_path(), global_mod.current_path)
shutil.copy(ngc.rel_path(), current_path)
logging.info("Cores merged.")
......@@ -25,7 +25,6 @@ import os
import sys
import importlib
from hdlmake import global_mod
from hdlmake.srcfile import SourceFileFactory
from .action import Action
......@@ -68,10 +67,10 @@ class GenerateRemoteSynthesisMakefile(Action):
files = self.modules_pool.build_file_set()
sff = SourceFileFactory()
files.add(sff.new(top_mod.syn_project, module=None))
files.add(sff.new(top_mod.syn_project, module=self.top_module))
tool_object.generate_remote_synthesis_makefile(files=files, name=top_mod.syn_name,
cwd=global_mod.current_path, user=self.env["rsynth_user"],
cwd=top_mod.url, user=self.env["rsynth_user"],
server=self.env["rsynth_server"])
logging.info("Remote synthesis makefile generated.")
......
......@@ -27,7 +27,6 @@ import importlib
from hdlmake.dep_file import DepFile
import hdlmake.new_dep_solver as dep_solver
from hdlmake import global_mod
from .action import Action
......
......@@ -25,8 +25,6 @@ import logging
import sys
import importlib
from hdlmake import global_mod
from .action import Action
......@@ -70,8 +68,8 @@ class GenerateSynthesisMakefile(Action):
env.check_general()
env.check_tool(tool_object)
if global_mod.env[path_key]:
tool_path = global_mod.env[path_key]
if env[path_key]:
tool_path = env[path_key]
else:
tool_path = ""
......
......@@ -28,7 +28,6 @@ import importlib
from hdlmake.srcfile import SourceFileFactory
from hdlmake.dependable_file import DependableFile
from hdlmake import global_mod
from hdlmake.util import path
from .action import Action
......@@ -122,9 +121,9 @@ end sdb_meta_pkg;""")
for digit in syn_tool_version:
syn_tool_std_logic_vector.append("{0:04b}".format(int(digit)))
filled_template = template.substitute(repo_url=global_mod.top_module.url,
syn_module_name=global_mod.top_module.syn_top,
syn_commit_id=global_mod.top_module.revision,
filled_template = template.substitute(repo_url=self.top_module.url,
syn_module_name=self.top_module.syn_top,
syn_commit_id=self.top_module.revision,
syn_tool_name=tool.upper(),
syn_tool_version="0000"*(8-len(syn_tool_std_logic_vector))+''.join(syn_tool_std_logic_vector),
syn_tool_version_str=syn_tool_version,
......@@ -175,6 +174,11 @@ end sdb_meta_pkg;""")
fileset = self.modules_pool.build_file_set()
non_dependable = fileset.inversed_filter(DependableFile)
fileset.add(non_dependable)
privative_files = tool_object.supported_files(self.modules_pool.build_complete_file_set())
if privative_files:
logging.info("Privative / non-parseable files detected: %s" % len(privative_files))
fileset.add(privative_files)
sff = SourceFileFactory()
if self.options.generate_project_vhd:
......
......@@ -21,7 +21,6 @@
import os
from . import global_mod
from .util import path as path_mod
......@@ -81,11 +80,8 @@ class DepRelation(object):
class File(object):
def __init__(self, path, module=None):
self.path = path
if module is None:
self.module = global_mod.top_module
else:
assert not isinstance(module, basestring)
self.module = module
assert not isinstance(module, basestring)
self.module = module
@property
def name(self):
......@@ -101,7 +97,7 @@ class File(object):
def rel_path(self, dir=None):
if dir is None:
dir = global_mod.current_path
dir = os.getcwd()
return path_mod.relpath(self.path, dir)
def __str__(self):
......
......@@ -29,7 +29,6 @@ import os.path
from .util import path
from .util.termcolor import colored
from . import global_mod
_plain_print = print
......@@ -71,9 +70,6 @@ class Env(dict):
print.set_verbose(verbose)
# Check and determine general environment
self.check_general()
#tool_object = global_mod.tool_module.ToolControls()
#self._check_tool(tool_object)
#self._check_remote_tool(tool_object)
def _get(self, name):
......
......@@ -26,14 +26,13 @@ from tempfile import TemporaryFile
from subprocess import Popen, PIPE
from .constants import (GIT, GITSUBMODULE)
from .fetcher import Fetcher
from hdlmake import global_mod
class GitSubmodule(Fetcher):
def fetch(self, module):
if module.source != GITSUBMODULE:
raise ValueError("This backend should get git modules only.")
cur_dir = global_mod.current_path
cur_dir = module.pool.top_module.url
os.chdir(module.fetchto)
os.system("git submodule init")
os.system("git submodule update")
......@@ -46,7 +45,7 @@ class Git(Fetcher):
@staticmethod
def get_git_toplevel(module):
cur_dir = global_mod.current_path
cur_dir = module.pool.top_module.url
try:
os.chdir(path.rel2abs(module.path))
if not os.path.exists(".gitmodules"):
......@@ -64,7 +63,7 @@ class Git(Fetcher):
def get_git_submodules(module):
submodule_dir = path.rel2abs(module.path)
logging.debug("Checking git submodules in %s" % submodule_dir)
cur_dir = global_mod.current_path
cur_dir = module.pool.top_module.url
try:
os.chdir(submodule_dir)
......@@ -118,7 +117,7 @@ submodule.ip_cores/wr-cores.url=git://ohwr.org/hdl-core-lib/wr-cores.git
if not os.path.exists(module.fetchto):
os.mkdir(module.fetchto)
cur_dir = global_mod.current_path
cur_dir = module.pool.top_module.url
if module.branch is None:
module.branch = "master"
......@@ -165,7 +164,7 @@ submodule.ip_cores/wr-cores.url=git://ohwr.org/hdl-core-lib/wr-cores.git
@staticmethod
def check_commit_id(path):
cur_dir = global_mod.current_path
cur_dir = os.getcwd()
commit = None
stderr = TemporaryFile()
try:
......
......@@ -25,7 +25,6 @@ from tempfile import TemporaryFile
from subprocess import Popen, PIPE
from hdlmake.util import path
from .fetcher import Fetcher
from hdlmake import global_mod
class Svn(Fetcher):
......@@ -36,7 +35,7 @@ class Svn(Fetcher):
if not os.path.exists(module.fetchto):
os.mkdir(module.fetchto)
cur_dir = global_mod.current_path
cur_dir = module.pool.top_module.url
os.chdir(module.fetchto)
basename = path.url_basename(module.url)
......@@ -62,7 +61,7 @@ class Svn(Fetcher):
@staticmethod
def check_revision_number(path):
cur_dir = global_mod.current_path
cur_dir = os.getcwd()
revision = None
stderr = TemporaryFile()
......
......@@ -23,10 +23,5 @@
#
options = None
top_module = None
mod_pool = None
sim_tool = None
env = None
makefile_writer = None
current_path = None
......@@ -27,7 +27,6 @@ import logging
from .manifest_parser import Manifest, ManifestParser
from .util import path as path_mod
from . import global_mod
from . import fetch
......@@ -97,7 +96,7 @@ class Module(object):
self.sim_only_files = None
self.sim_pre_script = None
self.sim_post_script = None
self.top_module = None
self.top_module = pool.get_top_module()
self.commit_id = None
self.hw_tcl_filename = None
......@@ -198,7 +197,7 @@ class Module(object):
manifest_parser = ManifestParser()
manifest_parser.add_arbitrary_code(global_mod.options.arbitrary_code)
#manifest_parser.add_arbitrary_code(self.pool.top_module.options.arbitrary_code)
if self.manifest is None:
logging.debug("No manifest found in module "+str(self))
......@@ -209,7 +208,7 @@ class Module(object):
if self.parent is None:
extra_context = {}
else:
extra_context = dict(global_mod.top_module.manifest_dict) # copy the dictionary
extra_context = dict(self.top_module.manifest_dict) # copy the dictionary
del extra_context["modules"]
del extra_context["files"]
del extra_context["include_dirs"]
......@@ -289,15 +288,6 @@ class Module(object):
makefiles_paths = self._make_list_of_paths(mkFileList)
self.incl_makefiles.extend(makefiles_paths)
#if self.vlog_opt == "":
# self.vlog_opt = global_mod.top_module.vlog_opt
#if self.vcom_opt == "":
# self.vcom_opt = global_mod.top_module.vcom_opt
#if self.vsim_opt == "":
# self.vsim_opt = global_mod.top_module.vsim_opt
# if self.vmap_opt == "":
# self.vmap_opt = global_mod.top_module.vmap_opt
self.library = self.manifest_dict["library"]
self.include_dirs = []
if self.manifest_dict["include_dirs"] is not None:
......@@ -446,7 +436,7 @@ class Module(object):
m.parse_manifest()
m.process_manifest()
if self == global_mod.top_module:
if self == self.top_module:
revision = fetch.Svn.check_revision_number(self.path)
if revision is None:
commit = fetch.Git.check_commit_id(self.path)
......
......@@ -26,7 +26,6 @@ import logging
from subprocess import PIPE, Popen
import sys
from . import global_mod
from . import new_dep_solver as dep_solver
from .util import path as path_mod
from . import fetch
......@@ -38,6 +37,10 @@ class ModulePool(list):
self.top_module = None
self.global_fetch = os.getenv("HDLMAKE_COREDIR")
self._deps_solved = False
self.env = None
def set_environment(self, env):
self.env = env
def get_module_by_path(self, path):
"""Get instance of Module being stored at a given location"""
......@@ -98,19 +101,18 @@ class ModulePool(list):
pool=self)
self._add(new_module)
if not self.top_module:
global_mod.top_module = new_module
self.top_module = new_module
new_module.parse_manifest()
new_module.process_manifest()
url = self._guess_origin(global_mod.top_module.path)
url = self._guess_origin(self.top_module.path)
if url:
global_mod.top_module.url = url
self.top_module.url = url
return new_module
def _guess_origin(self, path):
"""Guess origin (git, svn, local) of a module at given path"""
cwd = global_mod.current_path
cwd = self.top_module.url
try:
os.chdir(path)
git_out = Popen("git config --get remote.origin.url", stdout=PIPE, shell=True, close_fds=True)
......@@ -169,7 +171,7 @@ class ModulePool(list):
while len(fetch_queue) > 0:
cur_mod = fetch_queue.pop()
if flatten is True:
cur_mod.fetchto = global_mod.top_module.fetchto
cur_mod.fetchto = self.top_module.fetchto
new_modules = []
if unfetched_only:
if cur_mod.isfetched:
......@@ -196,10 +198,7 @@ class ModulePool(list):
def build_file_set(self):
from srcfile import SourceFileSet
build_files = SourceFileSet()
if global_mod.options.no_parse == False:
build_files.add(self.build_limited_file_set())
else:
build_files.add(self.build_complete_file_set())
build_files.add(self.build_limited_file_set())
return build_files
def build_complete_file_set(self):
......@@ -212,13 +211,11 @@ class ModulePool(list):
def build_limited_file_set(self):
top_entity = self.top_module.top_module
tool_object = global_mod.tool_module.ToolControls()
self.solve_dependencies()
all_files = self.build_complete_file_set()
from srcfile import SourceFileSet
source_files = SourceFileSet()
source_files.add(dep_solver.make_dependency_set(all_files, top_entity))
source_files.add(tool_object.supported_files(all_files))
return source_files
def get_top_module(self):
......
......@@ -26,7 +26,6 @@ import logging
from .dep_file import DepFile
from .srcfile import VHDLFile, VerilogFile, SVFile
from . import global_mod
class DepParser(object):
def __init__(self, dep_file):
......@@ -52,24 +51,6 @@ class ParserFactory(object):
else :
raise ValueError("Unrecognized file format : %s" % dep_file.file_path)
# class DepSolver(object):
# def solve(self, vhdl_files):
# for f in vhdl_files:
# logging.debug("solving deps for " + f.path)
# if f.dep_requires:
# for req in f.dep_requires:
# pf = self._find_provider_file(req=req, vhdl_file=f, fset=vhdl_files)
# assert isinstance(pf, SourceFile)
# if not pf:
# logging.error("Missing dependency in file "+str(f)+": " + req[0]+'.'+req[1])
# else:
# logging.debug("%s depends on %s" % (f.path, pf.path))
# if pf.path != f.path:
# f.dep_depends_on.append(pf)
# #get rid of duplicates by making a set from the list and vice versa
# f.dep_depends_on = list(set(f.dep_depends_on))
# f.dep_resolved = True
def solve(fileset):
from .srcfile import SourceFileSet
......@@ -77,24 +58,12 @@ def solve(fileset):
assert isinstance(fileset, SourceFileSet)
fset = fileset.filter(DepFile)
# for fle in fset:
# print(fle.path)
# for rel in fle.rels:
# print('\t' + str(rel))
not_satisfied = 0
for investigated_file in fset:
logging.debug("Dependency solver investigates %s (%d relations)" % (investigated_file, len(investigated_file.rels)))
for rel in investigated_file.rels:
if rel.direction is DepRelation.PROVIDE: # PROVIDE relations dont have to be satisfied
continue
if rel.rel_type is DepRelation.INCLUDE: # INCLUDE are already solved by preprocessor
continue
if rel.library() in global_mod.tool_module.ToolControls().get_standard_libraries(): # dont care about standard libs
continue
satisfied_by = set()
for dep_file in fset:
# if dep_file is investigated_file:
# continue
if dep_file.satisfies(rel):
if dep_file is not investigated_file:
investigated_file.depends_on.add(dep_file)
......@@ -115,7 +84,7 @@ def solve(fileset):
logging.info("Dependencies solved")
def make_dependency_sorted_list(fileset, purge_unused=True):
def make_dependency_sorted_list(fileset, purge_unused=True, reverse=False):
"""Sort files in order of dependency.
Files with no dependencies first.
All files that another depends on will be earlier in the list."""
......@@ -124,8 +93,8 @@ def make_dependency_sorted_list(fileset, purge_unused=True):
dependable.sort(key=lambda f: f.file_path.lower()) # Not necessary, but will tend to group files more nicely in the output.
dependable.sort(key=DepFile.get_dep_level)
sorted_list = non_dependable + dependable
#if global_mod.options.reverse == True:
# sorted_list = list(reversed(sorted_list))
if reverse:
sorted_list = list(reversed(sorted_list))
return sorted_list
def make_dependency_set(fileset, top_level_entity):
......
......@@ -30,7 +30,6 @@ import os
import string
from subprocess import Popen, PIPE
from hdlmake import global_mod
import hdlmake.new_dep_solver as dep_solver
from hdlmake.makefile_writer import MakefileWriter
......@@ -455,7 +454,7 @@ mrproper:
self.add_property("Create Binary Configuration File", "true")
def _set_values_from_manifest(self):
tm = global_mod.mod_pool.get_top_module()
tm = self.top_mod
if tm.syn_family == None:
tm.syn_family = FAMILY_NAMES.get(tm.syn_device[0:4].upper())
if tm.syn_family == None:
......
......@@ -30,7 +30,6 @@ import logging
import sys
import string
from hdlmake import global_mod
from hdlmake.makefile_writer import MakefileWriter
......@@ -76,13 +75,12 @@ class ToolControls(MakefileWriter):
def generate_simulation_makefile(self, fileset, top_module):
from hdlmake.srcfile import VerilogFile, VHDLFile
#from ..ise import XilinxsiminiReader
make_preambule_p1 = """## variables #############################
PWD := $(shell pwd)
TOP_MODULE := """ + top_module.top_module + """
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := """ + XilinxsiminiReader.xilinxsim_ini_dir() + """
XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) + """
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
......@@ -250,54 +248,9 @@ isim.wdb isim_proj isim_proj.*
return ' '.join(ret)
class XilinxsiminiReader(object):
def __init__(self, path=None):
if path is None:
path = self.xilinxsim_ini_dir() + "/xilinxsim.ini"
self.path = path
# Parse the xilinxsim.ini file to get the referenced libraries
def get_libraries(self):
libs = []
try:
ini = open(self.path, "r")
except Exception:
raise RuntimeError("Can't open existing xilinxsim.ini file")
#p.info("Reading 'xilinxsim.ini' located in: '"+ str(self.path))
# Read loggical libraries name, skipping comments and other
#possible sections
for line in ini:
# Read line by line, skipping comments and striping newline
line = line.split('--')[0].strip()
# Still in comments section
if line == "":
continue
# Not in comments section. Library section:
#<logical_library> = <phisical_path>
line = line.split('=')
lib = line[0].strip()
libs.append(lib.lower())
return libs
@staticmethod
def xilinxsim_ini_dir():
# Does not really need this
# try:
# host_platform = os.environ["HOST_PLATFORM"]
# except KeyError:
# logging.error("Please set the environment variable HOST_PLATFORM")
# quit()
#if global_mod.env["xilinx"]:
# xilinx_dir = global_mod.env["xilinx"]
if global_mod.env["isim_path"]:
xilinx_dir = str(os.path.join(global_mod.env["isim_path"],"..",".."))
def __get_xilinxsim_ini_dir(self, env):
if env["isim_path"]:
xilinx_dir = str(os.path.join(env["isim_path"],"..",".."))
else:
logging.error("Cannot calculate xilinx tools base directory")
quit()
......@@ -309,7 +262,7 @@ class XilinxsiminiReader(object):
else:
os_prefix = 'lin'
if global_mod.env["architecture"] == 32:
if env["architecture"] == 32:
arch_sufix = ''
else:
arch_sufix = '64'
......
......@@ -26,7 +26,6 @@ import string
import os
import logging
from hdlmake import global_mod
from hdlmake.makefile_writer import MakefileWriter
......@@ -152,7 +151,7 @@ mrproper: clean
print('javi checkpoint 0')
from hdlmake.srcfile import VerilogFile
for f in global_mod.top_module.incl_makefiles:
for f in top_module.incl_makefiles:
self.writeln("include " + f)
target_list = []
for vl in fileset.filter(VerilogFile):
......@@ -175,14 +174,14 @@ mrproper: clean
print('javi target_list', target_list)
sim_only_files = []
for m in global_mod.mod_pool:
for m in modules_pool:
for f in m.sim_only_files:
sim_only_files.append(f.name)
print('javi sim_only_files', sim_only_files)
# bit file targets are those that are only used in simulation
bit_targets = []
for m in global_mod.mod_pool:
for m in modules_pool:
bit_targets = bit_targets + list(m.bit_file_targets)
print('javi bit_targets', bit_targets)
......@@ -199,9 +198,9 @@ mrproper: clean
if not os.path.exists("%s.ucf" % bt):
logging.warning("The file %s.ucf doesn't exist!" % bt)
self.writeln(bt+".bit:\t"+bt+".v $("+bt+"syn_deps) "+bt+".ucf")
part=(global_mod.top_module.syn_device+'-'+
global_mod.top_module.syn_package+
global_mod.top_module.syn_grade)
part=(top_module.syn_device+'-'+
top_module.syn_package+
top_module.syn_grade)
self.writeln("\tPART="+part+" $(SYNTH) "+bt+" $^")
self.writeln("\tmv _xilinx/"+bt+".bit $@")
......
......@@ -25,7 +25,6 @@ from __future__ import print_function
import xml.dom.minidom
import os
from hdlmake import global_mod
from ..common.sim_makefile_support import VsimMakefileWriter
XmlImpl = xml.dom.minidom.getDOMImplementation()
......@@ -61,8 +60,8 @@ class ToolControls(VsimMakefileWriter):
self.vcom_flags.extend(["-modelsimini", "modelsim.ini"])
self.vlog_flags.extend(["-modelsimini", "modelsim.ini"])
self.vmap_flags.extend(["-modelsimini", "modelsim.ini"])
if global_mod.env["modelsim_path"]:
modelsim_ini_path = os.path.join(global_mod.env["modelsim_path"], "..")
if top_module.pool.env["modelsim_path"]:
modelsim_ini_path = os.path.join(top_module.pool.env["modelsim_path"], "..")
else:
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
......
......@@ -23,7 +23,6 @@
from __future__ import print_function
import os
import logging
from hdlmake import global_mod
def url_parse(url):
......@@ -115,7 +114,7 @@ def is_abs_path(path):
def relpath(p1, p2=None):
if p2 is None:
p2 = global_mod.current_path
p2 = os.getcwd()
if p1 == p2:
return '.'
p1, p2 = p2, p1
......@@ -143,7 +142,7 @@ def rel2abs(path, base=None):
@return the relative path of path from base
"""
if base is None:
base = global_mod.current_path
base = os.getcwd()
if os.path.isabs(path):
return path
retval = os.path.join(base, path)
......
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