Commit a8ffeb23 authored by Tristan Gingold's avatar Tristan Gingold

Add a testsuite.

parent 7d7aad4b
[run]
source = ../hdlmake
omit = ../hdlmake/util/termcolor.py
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH :=
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
action = "synthesis"
language = "vhdl"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "ise"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := my_ini
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
modelsim_ini_path="my_ini"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := fake_bin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
sim_path="fake_bin"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
language = "vhdl"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
simulation:
echo # Active-HDL command file, generated by HDLMake > run.command
echo # Create library and set as default target >> run.command
echo alib work >> run.command
echo set worklib work >> run.command
echo # Compiling HDL source files >> run.command
echo acom "../files/gate.vhdl" >> run.command
vsimsa -do run.command
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) run.command library.cfg work
clean:
del /s /q /f $(CLEAN_TARGETS)
@-rmdir /s /q $(CLEAN_TARGETS) >nul 2>&1
mrproper: clean
del /s /q /f *.vcd *.asdb
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="active_hdl"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).ldf
TOOL_PATH :=
TCL_INTERPRETER := diamondc
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := anfpga
SYN_PACKAGE := ff
SYN_GRADE := 3
TCL_CREATE := prj_project new -name $(PROJECT) -impl $(PROJECT) -dev ANFPGA3FF -synthesis "synplify"
TCL_OPEN := prj_project open $(PROJECT).ldf
TCL_SAVE := prj_project save
TCL_CLOSE := prj_project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "prj_src add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo source files.tcl >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo prj_run PAR -impl $(PROJECT) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: project par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo prj_run Export -impl $(PROJECT) -task Bitgen >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.sty $(PROJECT)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.jed
.PHONY: mrproper clean all
action = "synthesis"
syn_tool="diamond"
syn_device="anfpga"
syn_grade="3"
syn_package="ff"
syn_project="gate"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
GHDL := ghdl
GHDL_OPT :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
$(GHDL) -e $(GHDL_OPT) $(TOP_MODULE)
work/gate/.gate_vhdl: ../files/gate.vhdl
$(GHDL) -a $(GHDL_OPT) $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) *.cf *.o $(TOP_MODULE) work
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="ghdl"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate2
PWD := $(shell pwd)
PROJECT := gate2
PROJECT_FILE := $(PROJECT).
TOOL_PATH :=
TCL_INTERPRETER := yosys -c
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := iCE40
SYN_DEVICE := ice40
SYN_PACKAGE := ff
SYN_GRADE := 3
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VerilogFile := \
../files/gate2.v
files.tcl:
@$(foreach sourcefile, $(SOURCES_VerilogFile), echo "read_verilog $(sourcefile)" >> $@ &)
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
synthesize.tcl:
echo yosys -import >> $@
echo source files.tcl >> $@
echo synth_ice40 -top $(TOP_MODULE) -blif $(PROJECT).blif >> $@
synthesize: files.tcl synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo catch {exec arachne-pnr -d $(SYN_DEVICE) -P $(SYN_PACKAGE) -p $(SOURCES_PCFFile) -o $(PROJECT).asc $(PROJECT).blif} >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo catch {exec icepack $(PROJECT).asc $(PROJECT).bin} >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) $(PROJECT).asc $(PROJECT).blif
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf $(PROJECT).bin
.PHONY: mrproper clean all
action = "synthesis"
syn_tool="icestorm"
syn_device="ice40"
syn_grade="3"
syn_package="ff"
syn_project="gate2"
top_module = "gate2"
files = [ "../files/gate2.v" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
TOP_MODULE := gate_tb
FUSE_OUTPUT ?= isim_proj
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := ../files/gate_tb.v \
VERILOG_OBJ := work/gate_tb/.gate_tb_v \
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
LIBS := work
LIB_IND := work/.work
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
cp $< .
fuse:
fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
work/.work:
(mkdir -p work && touch work/.work && echo work=work >> xilinxsim.ini) || rm -rf work
work/gate_tb/.gate_tb_v: ../files/gate_tb.v ../files/gate.vhdl
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../files $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate_vhdl: ../files/gate.vhdl work/gate/.gate
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate:
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb isim_proj isim_proj.*
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="isim"
top_module = "gate_tb"
files = [ "../files/gate.vhdl", "../files/gate_tb.v" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH :=
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
extra_line: makefile differs...
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH :=
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
action = "synthesis"
language = "vhdl"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "ise"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate2
PWD := $(shell pwd)
IVERILOG_OPT :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := ../files/gate2.v \
VERILOG_OBJ := work/gate2/.gate2_v \
VHDL_SRC :=
VHDL_OBJ :=
simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)
iverilog $(IVERILOG_OPT) -s $(TOP_MODULE) -o $(TOP_MODULE).vvp -c run.command
include_dirs:
echo "# IVerilog command file, generated by HDLMake" > run.command
work/gate2/.gate2_v: ../files/gate2.v
echo $< >> run.command
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) run.command ivl_vhdl_work work
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.vvp
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="iverilog"
top_module = "gate2"
files = [ "../files/gate2.v" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).prjx
TOOL_PATH :=
TCL_INTERPRETER := libero SCRIPT:
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := anfpga
SYN_PACKAGE := ff
SYN_GRADE := 3
TCL_CREATE := new_project -location {./gate} -name {gate} -hdl {VHDL} -family {ProASIC3} -die {ANFPGA} -package {FF} -speed {3} -die_voltage {1.5}
TCL_OPEN := open_project -file {$(PROJECT)/$(PROJECT_FILE)}
TCL_SAVE := save_project
TCL_CLOSE := close_project
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
SOURCES_SDCFile := \
syn.sdc
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "create_links -hdl_source $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_SDCFile), echo "create_links -sdc $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo source files.tcl >> $@
echo organize_tool_files -tool {SYNTHESIZE} -file {syn.sdc} -module {$(TOP_MODULE)::work} -input_type {constraint} >> $@
echo organize_tool_files -tool {COMPILE} -file {syn.sdc} -module {$(TOP_MODULE)::work} -input_type {constraint} >> $@
echo set_root -module {$(TOP_MODULE)::work} >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo update_and_run_tool -name {GENERATEPROGRAMMINGDATA} >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) $(PROJECT)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.pdb *.stp
.PHONY: mrproper clean all
action = "synthesis"
syn_tool="libero"
syn_device="anfpga"
syn_grade="3"
syn_package="ff"
syn_project="gate"
top_module = "gate"
# Not reliable.
#files = [ "../files/gate.vhdl", "syn.sdc", "comp.pdc" ]
files = [ "../files/gate.vhdl", "syn.sdc" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).ppr
TOOL_PATH :=
TCL_INTERPRETER := planAhead -mode tcl -source
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := create_project $(PROJECT) ./
TCL_OPEN := open_project $(PROJECT_FILE)
TCL_CLOSE := exit
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "add_files -norecurse $(sourcefile); set_property IS_GLOBAL_INCLUDE 1 [get_files $(sourcefile)]" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo # project properties >> $@
echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
echo set_property "target_language" "vhdl" [current_project] >> $@
echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
echo source files.tcl >> $@
echo update_compile_order -fileset sources_1 >> $@
echo update_compile_order -fileset sim_1 >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo # synthesize properties >> $@
echo reset_run synth_1 >> $@
echo launch_runs synth_1 >> $@
echo wait_on_run synth_1 >> $@
echo set result [get_property STATUS [get_runs synth_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo # par properties >> $@
echo reset_run impl_1 >> $@
echo launch_runs impl_1 >> $@
echo wait_on_run impl_1 >> $@
echo set result [get_property STATUS [get_runs impl_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo launch_runs impl_1 -to_step Bitgen >> $@
echo wait_on_run impl_1 >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) planAhead_* planAhead.* .Xil $(PROJECT).cache $(PROJECT).data $(PROJECT).runs $(PROJECT).ppr
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin
.PHONY: mrproper clean all
action = "synthesis"
language = "vhdl"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "planahead"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
action = "synthesis"
language = "vhdl"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
VCOM_FLAGS := -quiet -2008
VSIM_FLAGS :=
VLOG_FLAGS := -quiet
VMAP_FLAGS :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) :
$(VHDL_OBJ): $(LIB_IND)
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) *.asdb
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="riviera"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xpr
TOOL_PATH :=
TCL_INTERPRETER := vivado -mode tcl -source
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := xc7z030
SYN_PACKAGE := ffg676
SYN_GRADE := -2
TCL_CREATE := create_project $(PROJECT) ./
TCL_OPEN := open_project $(PROJECT_FILE)
TCL_CLOSE := exit
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "add_files -norecurse $(sourcefile); set_property IS_GLOBAL_INCLUDE 1 [get_files $(sourcefile)]" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo # project properties >> $@
echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
echo set_property "target_language" "vhdl" [current_project] >> $@
echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
echo source files.tcl >> $@
echo update_compile_order -fileset sources_1 >> $@
echo update_compile_order -fileset sim_1 >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo # synthesize properties >> $@
echo reset_run synth_1 >> $@
echo launch_runs synth_1 >> $@
echo wait_on_run synth_1 >> $@
echo set result [get_property STATUS [get_runs synth_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo # par properties >> $@
echo reset_run impl_1 >> $@
echo launch_runs impl_1 >> $@
echo wait_on_run impl_1 >> $@
echo set result [get_property STATUS [get_runs impl_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo launch_runs impl_1 -to_step write_bitstream >> $@
echo wait_on_run impl_1 >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb *.dmp $(PROJECT).cache $(PROJECT).data work $(PROJECT).runs $(PROJECT).hw $(PROJECT).ip_user_files $(PROJECT_FILE)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin
.PHONY: mrproper clean all
action = "synthesis"
language = "vhdl"
syn_device = "xc7z030"
syn_grade = "-2"
syn_package = "ffg676"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "vivado"
files = [ "../files/gate.vhdl" ]
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
xelab -debug all $(TOP_MODULE) -s $(TOP_MODULE)
work/gate/.gate_vhdl: ../files/gate.vhdl
xvhdl $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb work xsim.dir
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.wdb *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="vivado_sim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
fetchto = "ipcores"
files = [ "../files/gate.vhdl" ]
modules = { "git" : "git@test.org:tester/module1.git" }
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
fetchto = "ipcores"
files = [ "../files/gate.vhdl" ]
modules = { "svn" : "http://test.org:tester/module1" }
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
fetchto = "ipcores"
files = [ "../files/gate.vhdl" ]
modules = { "gitsm" : "git@test.org:tester/module1.git" }
entity gate is
port (o : out bit;
i : in bit);
end gate;
architecture behav of gate is
begin
o <= not i;
end behav;
module gate2(input i, output o);
assign o = ~i;
endmodule
module gate_tb;
reg i, o;
gate dut(.i(i), .o(o));
initial begin
i <= 0;
# 1;
$stop;
end
endmodule
#!/usr/bin/env python
import os
import sys
import shutil
argv = sys.argv[1:]
if len(argv) == 0:
print("fake git version 0.0")
sys.exit(1)
if argv[0] == 'clone':
print("fake git clone: {}".format(argv[1:]))
if len(argv) == 2:
# Get the basename of the module
name = argv[1]
name = name[name.rfind('/') + 1:-4]
modpath = os.path.join(os.path.dirname(__file__), '..', 'modules', name)
if os.path.exists(name):
sys.exit(0)
print("fake git cloning {} from {}".format(name, modpath))
# Copy all the files
shutil.copytree(modpath, name)
sys.exit(0)
else:
print("unhandled fake git clone")
sys.exit(1)
elif argv[0] == 'submodule':
if argv[1:] == ['init']:
sys.exit(0)
elif argv[1:] == ['update', '--recursive']:
sys.exit(0)
print("fake git unknown command: {}".format(argv))
sys.exit(1)
#!/usr/bin/env python
import os
import sys
import shutil
if len(sys.argv) == 1:
print("fake svn version 0.0")
sys.exit(1)
if sys.argv[1] == 'checkout':
print("fake svn checkout: {}".format(sys.argv[2:]))
if len(sys.argv) == 4:
# Get the basename of the module
name = sys.argv[2]
name = name[name.rfind('/') + 1:]
assert name == sys.argv[3]
modpath = os.path.join(os.path.dirname(__file__), '..', 'modules', name)
if os.path.exists(name):
sys.exit(0)
print("fake svn checkout {} from {}".format(name, modpath))
# Copy all the files
shutil.copytree(modpath, name)
sys.exit(0)
else:
print("unhandled fake svn checkout")
sys.exit(1)
else:
print("fake svn unknown command: {}".format(sys.argv[1:]))
sys.exit(1)
entity mod1 is
port (i : bit;
o : out bit);
end mod1;
architecture arch of mod1 is
begin
o <= i;
end arch;
# HDLmake testsuite
# Just run 'pytest' in this directory.
import hdlmake.__main__
import os
import os.path
import pytest
import shutil
class Config(object):
def __init__(self, path=None, check_windows=False):
self.path = path
self.prev_env_path = os.environ['PATH']
self.prev_check_windows = hdlmake.util.shell.check_windows
self.check_windows = check_windows
def __enter__(self):
os.environ['PATH'] = ("../linux_fakebin:"
+ os.path.abspath('linux_fakebin') + ':'
+ self.prev_env_path)
if self.path is not None:
os.chdir(self.path)
hdlmake.util.shell.check_windows = (lambda : self.check_windows)
def __exit__(self, *_):
if self.path is not None:
os.chdir("..")
os.environ['PATH'] = self.prev_env_path
hdlmake.util.shell.check_windows = self.prev_check_windows
def compare_makefile():
ref = open('Makefile.ref', 'r').read()
out = open('Makefile', 'r').read()
assert out == ref
os.remove('Makefile')
def run_compare(**kwargs):
with Config(**kwargs) as _:
hdlmake.__main__.hdlmake([])
compare_makefile()
def test_makefile_001():
run_compare(path="001ise")
def test_makefile_002():
run_compare(path="002msim")
def test_makefile_003():
run_compare(path="003msim")
def test_makefile_004():
run_compare(path="004msim")
def test_fetch():
with Config(path="001ise") as _:
hdlmake.__main__.hdlmake(['fetch'])
def test_clean():
with Config(path="001ise") as _:
hdlmake.__main__.hdlmake(['clean'])
def test_list_mods():
with Config(path="001ise") as _:
hdlmake.__main__.hdlmake(['list-mods'])
def test_list_files():
with Config(path="001ise") as _:
hdlmake.__main__.hdlmake(['list-files'])
def test_noact():
with Config(path="005noact") as _:
hdlmake.__main__.hdlmake(['manifest-help'])
hdlmake.__main__.hdlmake(['list-files'])
def test_ahdl():
run_compare(path="006ahdl", check_windows=True)
def test_diamond():
run_compare(path="007diamond")
def test_ghdl():
run_compare(path="008ghdl")
def test_icestorm():
run_compare(path="009icestorm")
def test_isim():
with Config(path="010isim") as _:
hdlmake.__main__.hdlmake([])
ref = open('Makefile.ref', 'r').readlines()
out = open('Makefile', 'r').readlines()
# HDLmake make the path absolute. Remove this line.
out = [l for l in out if not l.startswith("XILINX_INI_PATH")]
assert out == ref
os.remove('Makefile')
def test_icarus():
run_compare(path="012icarus")
def test_libero():
run_compare(path="013libero")
def test_planahead():
run_compare(path="014planahead")
def test_quartus():
run_compare(path="015quartus")
def test_quartus016():
run_compare(path="016quartus_nofam")
def test_riviera():
run_compare(path="017riviera")
def test_vivado():
run_compare(path="018vivado")
def test_vivado_sim():
run_compare(path="019vsim")
def test_git_fetch():
with Config(path="020git_fetch") as _:
hdlmake.__main__.hdlmake(['fetch'])
shutil.rmtree('ipcores.old', ignore_errors=True)
shutil.move('ipcores', 'ipcores.old')
def test_svn_fetch():
with Config(path="021svn_fetch") as _:
hdlmake.__main__.hdlmake(['fetch'])
shutil.rmtree('ipcores')
def test_gitsm_fetch():
with Config(path="022gitsm_fetch") as _:
hdlmake.__main__.hdlmake(['fetch'])
shutil.rmtree('ipcores')
@pytest.mark.xfail
def test_xfail():
"""This is a self-consistency test: the test is known to fail"""
run_compare(path="011xfail")
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment