added another system ip component for altera

a69dfe21 · David Belohrad · ff130815 · a69dfe21
Commit a69dfe21 authored Nov 22, 2022 by David Belohrad
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altera_libs.py hdlmake/sourcefiles/altera_libs.py +1 -0

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--- a/hdlmake/sourcefiles/altera_libs.py
+++ b/hdlmake/sourcefiles/altera_libs.py
@@ -60,6 +60,7 @@ altera_system_libraries =\
     "oper_latch", "lcell", "altpll", "altlvds_rx",
     "altsyncram",
     "altlvds_tx", "dcfifo", "altaccumulate", "altmult_accum",
+     "dcfifo_mixed_widths",
     "altmult_add", "altfp_mult", "altsqrt", "altclklock",
     "altddio_bidir", "altdpram", "alt3pram", "parallel_add",
     "scfifo", "altshift_taps", "a_graycounter", "altsquare",