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Hdlmake
Commits
a1c642be
Commit
a1c642be
authored
May 31, 2019
by
Tristan Gingold
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testsuite: add tests for verilog parser.
parent
26217857
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11 changed files
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170 additions
and
0 deletions
+170
-0
.coveragerc
testsuite/.coveragerc
+3
-0
Makefile.ref
testsuite/024vlog_parser/Makefile.ref
+58
-0
Manifest.py
testsuite/024vlog_parser/Manifest.py
+7
-0
macros.v
testsuite/024vlog_parser/macros.v
+1
-0
vlog.v
testsuite/024vlog_parser/vlog.v
+20
-0
Makefile.ref
testsuite/025vlog_parser/Makefile.ref
+58
-0
Manifest.py
testsuite/025vlog_parser/Manifest.py
+8
-0
macros.v
testsuite/025vlog_parser/inc/macros.v
+1
-0
vlog.v
testsuite/025vlog_parser/vlog.v
+8
-0
isimgui
testsuite/linux_fakebin/isimgui
+0
-0
test_all.py
testsuite/test_all.py
+6
-0
No files found.
testsuite/.coveragerc
View file @
a1c642be
[run]
source = ../hdlmake
# Termcolor is an external module
# tree has external dependencies
omit = ../hdlmake/util/termcolor.py
../hdlmake/action/tree.py
testsuite/024vlog_parser/Makefile.ref
0 → 100644
View file @
a1c642be
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VMAP_FLAGS
:=
-modelsimini
modelsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
vlog.v
\
VERILOG_OBJ
:=
work/vlog/.vlog_v
\
VHDL_SRC
:=
VHDL_OBJ
:=
INCLUDE_DIRS
:=
LIBS
:=
work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
work/vlog/.vlog_v
:
vlog.v
\
macros.v
vlog
-work
work
$(VLOG_FLAGS)
${
INCLUDE_DIRS
}
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
sim_post_cmd
:
CLEAN_TARGETS
:=
$(LIBS)
modelsim.ini transcript
clean
:
rm
-rf
$(CLEAN_TARGETS)
mrproper
:
clean
rm
-rf
*
.vcd
*
.wlf
.PHONY
:
mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/024vlog_parser/Manifest.py
0 → 100644
View file @
a1c642be
action
=
"simulation"
sim_tool
=
"modelsim"
top_module
=
"gate"
files
=
[
"vlog.v"
]
testsuite/024vlog_parser/macros.v
0 → 100644
View file @
a1c642be
`define
MYWIRE
(
n
)
wire
n
;
testsuite/024vlog_parser/vlog.v
0 → 100644
View file @
a1c642be
`include
"macros.v"
module
gate
;
// My comment
`ifdef
MYWIRE
`MYWIRE
(
w
)
;
`endif
`ifndef
MYWIRE
wire
w2
;
`elsif
ALL
/* nothing. */
`else
wire
\
w3
;
`endif
endmodule
`pragma
protect
begin_protected
`pragma
none
`pragma
protect
end_protected
testsuite/025vlog_parser/Makefile.ref
0 → 100644
View file @
a1c642be
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
../linux_fakebin/..
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VMAP_FLAGS
:=
-modelsimini
modelsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
vlog.v
\
VERILOG_OBJ
:=
work/vlog/.vlog_v
\
VHDL_SRC
:=
VHDL_OBJ
:=
INCLUDE_DIRS
:=
+incdir+inc
LIBS
:=
work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
work/vlog/.vlog_v
:
vlog.v
\
inc/macros.v
vlog
-work
work
$(VLOG_FLAGS)
${
INCLUDE_DIRS
}
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
sim_post_cmd
:
CLEAN_TARGETS
:=
$(LIBS)
modelsim.ini transcript
clean
:
rm
-rf
$(CLEAN_TARGETS)
mrproper
:
clean
rm
-rf
*
.vcd
*
.wlf
.PHONY
:
mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/025vlog_parser/Manifest.py
0 → 100644
View file @
a1c642be
action
=
"simulation"
sim_tool
=
"modelsim"
top_module
=
"gate"
include_dirs
=
[
"inc"
]
files
=
[
"vlog.v"
]
testsuite/025vlog_parser/inc/macros.v
0 → 100644
View file @
a1c642be
`define
MYWIRE
(
n
)
wire
n
;
testsuite/025vlog_parser/vlog.v
0 → 100644
View file @
a1c642be
`include
"macros.v"
module
gate
;
// My comment
`ifdef
MYWIRE
`MYWIRE
(
w
)
;
`endif
endmodule
testsuite/linux_fakebin/isimgui
0 → 100644
View file @
a1c642be
testsuite/test_all.py
View file @
a1c642be
...
...
@@ -138,6 +138,12 @@ def test_gitsm_fetch():
def
test_xci
():
run_compare
(
path
=
"023xci"
)
def
test_vlog_parser
():
run_compare
(
path
=
"024vlog_parser"
)
def
test_vlog_parser025
():
run_compare
(
path
=
"025vlog_parser"
)
@
pytest
.
mark
.
xfail
def
test_xfail
():
"""This is a self-consistency test: the test is known to fail"""
...
...
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