Commit a1c642be authored by Tristan Gingold's avatar Tristan Gingold

testsuite: add tests for verilog parser.

parent 26217857
[run]
source = ../hdlmake
# Termcolor is an external module
# tree has external dependencies
omit = ../hdlmake/util/termcolor.py
../hdlmake/action/tree.py
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \
VHDL_SRC :=
VHDL_OBJ :=
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/vlog/.vlog_v: vlog.v \
macros.v
vlog -work work $(VLOG_FLAGS) ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "vlog.v" ]
`define MYWIRE(n) wire n;
`include "macros.v"
module gate;
// My comment
`ifdef MYWIRE
`MYWIRE(w);
`endif
`ifndef MYWIRE
wire w2;
`elsif ALL
/* nothing. */
`else
wire \
w3;
`endif
endmodule
`pragma protect begin_protected
`pragma none
`pragma protect end_protected
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \
VHDL_SRC :=
VHDL_OBJ :=
INCLUDE_DIRS := +incdir+inc
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/vlog/.vlog_v: vlog.v \
inc/macros.v
vlog -work work $(VLOG_FLAGS) ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
include_dirs=["inc"]
files = [ "vlog.v" ]
`include "macros.v"
module gate;
// My comment
`ifdef MYWIRE
`MYWIRE(w);
`endif
endmodule
......@@ -138,6 +138,12 @@ def test_gitsm_fetch():
def test_xci():
run_compare(path="023xci")
def test_vlog_parser():
run_compare(path="024vlog_parser")
def test_vlog_parser025():
run_compare(path="025vlog_parser")
@pytest.mark.xfail
def test_xfail():
"""This is a self-consistency test: the test is known to fail"""
......
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