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Hdlmake
Commit 9d5ff18d authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Refactor the way in which the simulations options are stored

parent 7f4143c1
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Inline Side-by-side
Showing with 26 additions and 43 deletions
hdlmake/srcfile.py
View file @ 9d5ff18d
......@@ -59,13 +59,9 @@ class VHDLFile(SourceFile):
"""This is the class providing the generic VHDL file"""
def __init__(self, path, module, library=None, vcom_opt=None):
def __init__(self, path, module, library=None):
SourceFile.__init__(self, path=path, module=module, library=library)
from hdlmake.vhdl_parser import VHDLParser
if not vcom_opt:
self.vcom_opt = ""
else:
self.vcom_opt = vcom_opt
self.parser = VHDLParser(self)
def _check_encryption(self):
......@@ -84,13 +80,9 @@ class VerilogFile(SourceFile):
"""This is the class providing the generic Verilog file"""
def __init__(self, path, module, library=None,
vlog_opt=None, include_dirs=None):
include_dirs=None):
SourceFile.__init__(self, path=path, module=module, library=library)
from hdlmake.vlog_parser import VerilogParser
if not vlog_opt:
self.vlog_opt = ""
else:
self.vlog_opt = vlog_opt
self.include_dirs = []
if include_dirs:
self.include_dirs.extend(include_dirs)
......@@ -387,7 +379,7 @@ class SourceFileSet(set):
def create_source_file(path, module, library=None,
vcom_opt=None, vlog_opt=None, include_dirs=None):
include_dirs=None):
"""Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type"""
if path is None or path == "":
......@@ -402,19 +394,16 @@ def create_source_file(path, module, library=None,
if extension in ['vhd', 'vhdl', 'vho']:
new_file = VHDLFile(path=path,
module=module,
library=library,
vcom_opt=vcom_opt)
library=library)
elif extension in ['v', 'vh', 'vo', 'vm']:
new_file = VerilogFile(path=path,
module=module,
library=library,
vlog_opt=vlog_opt,
include_dirs=include_dirs)
elif extension == 'sv' or extension == 'svh':
new_file = SVFile(path=path,
module=module,
library=library,
vlog_opt=vlog_opt,
include_dirs=include_dirs)
elif extension == 'wb':
new_file = WBGenFile(path=path, module=module)
......
hdlmake/tools/isim.py
View file @ 9d5ff18d
......@@ -119,13 +119,13 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir() +
else:
skip = True
return ' '.join(ret)
self.writeln("""VHPCOMP_FLAGS := -intstyle default \
-incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
__get_rid_of_isim_incdirs(
self.manifest_dict.get("vlog_opt", '')) + """
""")
default_options = ("-intstyle default -incremental " +
"-initfile xilinxsim.ini ")
self.writeln("VHPCOMP_FLAGS := " +
default_options + self.manifest_dict.get("vcom_opt", ''))
self.writeln("VLOGCOMP_FLAGS := " +
default_options + __get_rid_of_isim_incdirs(
self.manifest_dict.get("vlog_opt", '')))
def _makefile_sim_compilation(self):
"""Print the compile simulation target for Xilinx ISim"""
......@@ -206,8 +206,8 @@ fuse:
# incdir += " "
if vl_file.include_dirs:
self.write(' -i ')
self.write(' '.join(vl_file.include_dirs) + ' ')
self.writeln(vl_file.vlog_opt + " $<")
self.write(' '.join(vl_file.include_dirs))
self.writeln(" $<")
self.write("\t\t@" + shell.mkdir_command() + " $(dir $@)")
self.writeln(" && " + shell.touch_command() + " $@ \n\n")
self.write("\n")
......@@ -234,7 +234,6 @@ fuse:
"." + purename) + '\n')
self.writeln(
' '.join(["\t\tvhpcomp $(VHPCOMP_FLAGS)",
vhdl_file.vcom_opt,
"-work",
lib + "=." + shell.slash_char() + lib,
"$< "]))
......
hdlmake/tools/sim_makefile_support.py
View file @ 9d5ff18d
......@@ -73,18 +73,22 @@ class VsimMakefileWriter(ToolSim):
if not vlog_aux.startswith("+incdir+"):
ret.append(vlog_aux)
return ' '.join(ret)
self.vlog_flags.append(__get_rid_of_vsim_incdirs(
vcom_flags = ["-quiet", ]
vsim_flags = []
vlog_flags = ["-quiet", ]
vmap_flags = []
vlog_flags.append(__get_rid_of_vsim_incdirs(
self.manifest_dict.get("vlog_opt", '')))
self.vcom_flags.append(self.manifest_dict.get("vcom_opt", ''))
self.vmap_flags.append(self.manifest_dict.get("vmap_opt", ''))
self.vsim_flags.append(self.manifest_dict.get("vsim_opt", ''))
vcom_flags.append(self.manifest_dict.get("vcom_opt", ''))
vmap_flags.append(self.manifest_dict.get("vmap_opt", ''))
vsim_flags.append(self.manifest_dict.get("vsim_opt", ''))
for var, value in six.iteritems(self.custom_variables):
self.writeln("%s := %s" % (var, value))
self.writeln()
self.writeln("VCOM_FLAGS := %s" % (' '.join(self.vcom_flags)))
self.writeln("VSIM_FLAGS := %s" % (' '.join(self.vsim_flags)))
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
self.writeln("VCOM_FLAGS := %s" % (' '.join(vcom_flags)))
self.writeln("VSIM_FLAGS := %s" % (' '.join(vsim_flags)))
self.writeln("VLOG_FLAGS := %s" % (' '.join(vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(vmap_flags)))
def _makefile_sim_compilation(self):
"""Write a properly formatted Makefile for the simulator.
......@@ -147,15 +151,6 @@ class VsimMakefileWriter(ToolSim):
else: # the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
# self.write("\t\tvlog -work "+vlog.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vlog.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vlog.vlog_opt+" $<")
compile_template = string.Template(
"\t\tvlog -work ${library} $$(VLOG_FLAGS) "
"${sv_option} $${INCLUDE_DIRS} $$<")
......@@ -186,6 +181,6 @@ class VsimMakefileWriter(ToolSim):
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)",
vhdl.vcom_opt, "-work", lib, "$< "]))
"-work", lib, "$< "]))
self.writeln("\t\t@" + shell.mkdir_command() +
" $(dir $@) && " + shell.touch_command() + " $@ \n\n")
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