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9d06dd7c
Commit
9d06dd7c
authored
Nov 01, 2019
by
Tristan Gingold
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testsuite: add a test for system packages.
parent
0d414f05
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4 changed files
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84 additions
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+84
-0
Makefile.ref
testsuite/097sys_package/Makefile.ref
+60
-0
Manifest.py
testsuite/097sys_package/Manifest.py
+7
-0
gate.vhdl
testsuite/097sys_package/gate.vhdl
+12
-0
test_all.py
testsuite/test_all.py
+5
-0
No files found.
testsuite/097sys_package/Makefile.ref
0 → 100644
View file @
9d06dd7c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
TOP_MODULE
:=
gate
FUSE_OUTPUT
?=
isim_proj
VHPCOMP_FLAGS
:=
-intstyle
default
-incremental
-initfile
xilinxsim.ini
VLOGCOMP_FLAGS
:=
-intstyle
default
-incremental
-initfile
xilinxsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
VERILOG_OBJ
:=
VHDL_SRC
:=
gate.vhdl
\
VHDL_OBJ
:=
work/gate/.gate_vhdl
\
LIBS
:=
work
LIB_IND
:=
work/.work
simulation
:
xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ)
:
$(LIB_IND) xilinxsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) xilinxsim.ini
xilinxsim.ini
:
$(XILINX_INI_PATH)/xilinxsim.ini
cp
$<
.
fuse
:
fuse work.
$(TOP_MODULE)
-intstyle
ise
-incremental
-o
$(FUSE_OUTPUT)
work/.work
:
(
mkdir
-p
work
&&
touch
work/.work
&&
echo
work
=
work
>>
xilinxsim.ini
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
gate.vhdl work/gate/.gate
vhpcomp
$(VHPCOMP_FLAGS)
-work
work
=
./work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gate/.gate
:
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
sim_post_cmd
:
CLEAN_TARGETS
:=
$(LIBS)
xilinxsim.ini
$(LIBS)
fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb isim_proj isim_proj.
*
clean
:
rm
-rf
$(CLEAN_TARGETS)
mrproper
:
clean
rm
-rf
*
.vcd
.PHONY
:
mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/097sys_package/Manifest.py
0 → 100644
View file @
9d06dd7c
action
=
"simulation"
sim_tool
=
"isim"
top_module
=
"gate"
files
=
[
"gate.vhdl"
]
testsuite/097sys_package/gate.vhdl
0 → 100644
View file @
9d06dd7c
library
unisim
;
use
unisim
.
vcomponents
;
entity
gate
is
port
(
o
:
out
bit
;
i
:
in
bit
);
end
gate
;
architecture
behav
of
gate
is
begin
o
<=
not
i
;
end
behav
;
testsuite/test_all.py
View file @
9d06dd7c
...
@@ -512,6 +512,11 @@ def test_err_filetype():
...
@@ -512,6 +512,11 @@ def test_err_filetype():
def
test_multi_sat
():
def
test_multi_sat
():
run_compare
(
path
=
"093multi_sat"
)
run_compare
(
path
=
"093multi_sat"
)
def
test_sys_package_097
():
with
Config
(
path
=
"097sys_package"
)
as
_
:
hdlmake
.
main
.
hdlmake
([])
compare_makefile_xilinx
()
@
pytest
.
mark
.
xfail
@
pytest
.
mark
.
xfail
def
test_xfail
():
def
test_xfail
():
"""This is a self-consistency test: the test is known to fail"""
"""This is a self-consistency test: the test is known to fail"""
...
...
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