makefile.py: remove generated extra spaces.

99f1e918 · Tristan Gingold · 4468bbdc · 99f1e918 · 99f1e918 · 99f1e918
Commit 99f1e918 authored Nov 01, 2019 by Tristan Gingold
30 changed files
--- a/hdlmake/tools/makefile.py
+++ b/hdlmake/tools/makefile.py
@@ -105,7 +105,7 @@ class ToolMakefile(object):
    def _makefile_sim_file_touch_stamp(self):
        self.write("\t\t@" + shell.mkdir_command() + " $(dir $@)")
-        self.writeln(" && " + shell.touch_command()  + " $@ \n")
+        self.writeln(" && " + shell.touch_command()  + " $@\n")
    def makefile_check_tool(self, path_key):
        """Check if the binary is available in the O.S. environment"""

--- a/hdlmake/tools/makefilevsim.py
+++ b/hdlmake/tools/makefilevsim.py
@@ -105,7 +105,7 @@ class MakefileVsim(MakefileSim):
        self.writeln(
            "simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" %
            (' '.join(self.additional_deps)),)
-        self.writeln("$(VERILOG_OBJ) : " + ' '.join(self.additional_deps))
+        self.writeln("$(VERILOG_OBJ): " + ' '.join(self.additional_deps))
        self.writeln("$(VHDL_OBJ): $(LIB_IND) " + ' '.join(self.additional_deps))
        self.writeln()
        for filename, filesource in six.iteritems(self.copy_rules):

--- a/testsuite/002msim/Makefile.ref
+++ b/testsuite/002msim/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/003msim/Makefile.ref
+++ b/testsuite/003msim/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/004msim/Makefile.ref
+++ b/testsuite/004msim/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/008ghdl/Makefile.ref
+++ b/testsuite/008ghdl/Makefile.ref
--- a/testsuite/010isim/Makefile.ref
+++ b/testsuite/010isim/Makefile.ref
--- a/testsuite/012icarus/Makefile.ref
+++ b/testsuite/012icarus/Makefile.ref
--- a/testsuite/017riviera/Makefile.ref
+++ b/testsuite/017riviera/Makefile.ref
@@ -24,7 +24,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation:  $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : 
+$(VERILOG_OBJ): 
 $(VHDL_OBJ): $(LIB_IND) 
 work/.work:

--- a/testsuite/019vsim/Makefile.ref
+++ b/testsuite/019vsim/Makefile.ref
--- a/testsuite/024vlog_parser/Makefile.ref
+++ b/testsuite/024vlog_parser/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/025vlog_parser/Makefile.ref
+++ b/testsuite/025vlog_parser/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/027vhdl_parser/Makefile.ref
+++ b/testsuite/027vhdl_parser/Makefile.ref
@@ -27,7 +27,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/032manifest_vars/Makefile
+++ b/testsuite/032manifest_vars/Makefile
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/043local_fetch/Makefile.ref
+++ b/testsuite/043local_fetch/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/044files_dir/Makefile.ref
+++ b/testsuite/044files_dir/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/045incl_makefile/Makefile.ref
+++ b/testsuite/045incl_makefile/Makefile.ref
@@ -27,7 +27,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/046incl_makefiles/Makefile.ref
+++ b/testsuite/046incl_makefiles/Makefile.ref
@@ -28,7 +28,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/052svlog_parser/Makefile.ref
+++ b/testsuite/052svlog_parser/Makefile.ref
@@ -27,7 +27,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/057msim_windows/Makefile.ref
+++ b/testsuite/057msim_windows/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work\.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/060isim_windows/Makefile.ref
+++ b/testsuite/060isim_windows/Makefile.ref
--- a/testsuite/061err_nobin/Makefile.ref
+++ b/testsuite/061err_nobin/Makefile.ref
--- a/testsuite/076extra_modules/Makefile.ref
+++ b/testsuite/076extra_modules/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/079err_vlg_macro/Makefile.ref
+++ b/testsuite/079err_vlg_macro/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/081vlog_ifdef_elsif_else/Makefile.ref
+++ b/testsuite/081vlog_ifdef_elsif_else/Makefile.ref
@@ -27,7 +27,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/083icarus_include/Makefile.ref
+++ b/testsuite/083icarus_include/Makefile.ref
--- a/testsuite/087many_modules/Makefile.ref
+++ b/testsuite/087many_modules/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/088bad_file_abs/Makefile.ref
+++ b/testsuite/088bad_file_abs/Makefile.ref
@@ -25,7 +25,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/091library/Makefile.ref
+++ b/testsuite/091library/Makefile.ref
@@ -27,7 +27,7 @@ LIBS := sublib work
 LIB_IND := sublib/.sublib work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini

--- a/testsuite/093multi_sat/Makefile.ref
+++ b/testsuite/093multi_sat/Makefile.ref
@@ -29,7 +29,7 @@ LIBS := work
 LIB_IND := work/.work
 simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
-$(VERILOG_OBJ) : modelsim.ini
+$(VERILOG_OBJ): modelsim.ini
 $(VHDL_OBJ): $(LIB_IND) modelsim.ini
 modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini