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Hdlmake
Commits
99f1e918
Commit
99f1e918
authored
Nov 01, 2019
by
Tristan Gingold
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makefile.py: remove generated extra spaces.
parent
4468bbdc
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30 changed files
with
58 additions
and
58 deletions
+58
-58
makefile.py
hdlmake/tools/makefile.py
+1
-1
makefilevsim.py
hdlmake/tools/makefilevsim.py
+1
-1
Makefile.ref
testsuite/002msim/Makefile.ref
+2
-2
Makefile.ref
testsuite/003msim/Makefile.ref
+2
-2
Makefile.ref
testsuite/004msim/Makefile.ref
+2
-2
Makefile.ref
testsuite/008ghdl/Makefile.ref
+2
-2
Makefile.ref
testsuite/010isim/Makefile.ref
+1
-1
Makefile.ref
testsuite/012icarus/Makefile.ref
+1
-1
Makefile.ref
testsuite/017riviera/Makefile.ref
+2
-2
Makefile.ref
testsuite/019vsim/Makefile.ref
+1
-1
Makefile.ref
testsuite/024vlog_parser/Makefile.ref
+2
-2
Makefile.ref
testsuite/025vlog_parser/Makefile.ref
+2
-2
Makefile.ref
testsuite/027vhdl_parser/Makefile.ref
+3
-3
Makefile
testsuite/032manifest_vars/Makefile
+2
-2
Makefile.ref
testsuite/043local_fetch/Makefile.ref
+2
-2
Makefile.ref
testsuite/044files_dir/Makefile.ref
+2
-2
Makefile.ref
testsuite/045incl_makefile/Makefile.ref
+2
-2
Makefile.ref
testsuite/046incl_makefiles/Makefile.ref
+2
-2
Makefile.ref
testsuite/052svlog_parser/Makefile.ref
+3
-3
Makefile.ref
testsuite/057msim_windows/Makefile.ref
+2
-2
Makefile.ref
testsuite/060isim_windows/Makefile.ref
+1
-1
Makefile.ref
testsuite/061err_nobin/Makefile.ref
+1
-1
Makefile.ref
testsuite/076extra_modules/Makefile.ref
+2
-2
Makefile.ref
testsuite/079err_vlg_macro/Makefile.ref
+2
-2
Makefile.ref
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
+3
-3
Makefile.ref
testsuite/083icarus_include/Makefile.ref
+1
-1
Makefile.ref
testsuite/087many_modules/Makefile.ref
+2
-2
Makefile.ref
testsuite/088bad_file_abs/Makefile.ref
+2
-2
Makefile.ref
testsuite/091library/Makefile.ref
+3
-3
Makefile.ref
testsuite/093multi_sat/Makefile.ref
+4
-4
No files found.
hdlmake/tools/makefile.py
View file @
99f1e918
...
...
@@ -105,7 +105,7 @@ class ToolMakefile(object):
def
_makefile_sim_file_touch_stamp
(
self
):
self
.
write
(
"
\t\t
@"
+
shell
.
mkdir_command
()
+
" $(dir $@)"
)
self
.
writeln
(
" && "
+
shell
.
touch_command
()
+
" $@
\n
"
)
self
.
writeln
(
" && "
+
shell
.
touch_command
()
+
" $@
\n
"
)
def
makefile_check_tool
(
self
,
path_key
):
"""Check if the binary is available in the O.S. environment"""
...
...
hdlmake/tools/makefilevsim.py
View file @
99f1e918
...
...
@@ -105,7 +105,7 @@ class MakefileVsim(MakefileSim):
self
.
writeln
(
"simulation:
%
s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)"
%
(
' '
.
join
(
self
.
additional_deps
)),)
self
.
writeln
(
"$(VERILOG_OBJ)
: "
+
' '
.
join
(
self
.
additional_deps
))
self
.
writeln
(
"$(VERILOG_OBJ): "
+
' '
.
join
(
self
.
additional_deps
))
self
.
writeln
(
"$(VHDL_OBJ): $(LIB_IND) "
+
' '
.
join
(
self
.
additional_deps
))
self
.
writeln
()
for
filename
,
filesource
in
six
.
iteritems
(
self
.
copy_rules
):
...
...
testsuite/002msim/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/003msim/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/004msim/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/008ghdl/Makefile.ref
View file @
99f1e918
testsuite/010isim/Makefile.ref
View file @
99f1e918
testsuite/012icarus/Makefile.ref
View file @
99f1e918
testsuite/017riviera/Makefile.ref
View file @
99f1e918
...
...
@@ -24,7 +24,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
$(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
$(VERILOG_OBJ)
:
$(VHDL_OBJ)
:
$(LIB_IND)
work/.work
:
...
...
testsuite/019vsim/Makefile.ref
View file @
99f1e918
testsuite/024vlog_parser/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/025vlog_parser/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/027vhdl_parser/Makefile.ref
View file @
99f1e918
...
...
@@ -27,7 +27,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/032manifest_vars/Makefile
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/043local_fetch/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/044files_dir/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/045incl_makefile/Makefile.ref
View file @
99f1e918
...
...
@@ -27,7 +27,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/046incl_makefiles/Makefile.ref
View file @
99f1e918
...
...
@@ -28,7 +28,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/052svlog_parser/Makefile.ref
View file @
99f1e918
...
...
@@ -27,7 +27,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/057msim_windows/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work
\.
work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/060isim_windows/Makefile.ref
View file @
99f1e918
testsuite/061err_nobin/Makefile.ref
View file @
99f1e918
testsuite/076extra_modules/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/079err_vlg_macro/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
View file @
99f1e918
...
...
@@ -27,7 +27,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/083icarus_include/Makefile.ref
View file @
99f1e918
testsuite/087many_modules/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/088bad_file_abs/Makefile.ref
View file @
99f1e918
...
...
@@ -25,7 +25,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/091library/Makefile.ref
View file @
99f1e918
...
...
@@ -27,7 +27,7 @@ LIBS := sublib work
LIB_IND
:=
sublib/.sublib work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
testsuite/093multi_sat/Makefile.ref
View file @
99f1e918
...
...
@@ -29,7 +29,7 @@ LIBS := work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
...
...
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