Commit 98943d10 authored by Tristan Gingold's avatar Tristan Gingold

makefilesim, makefilevsim: factorize code.

parent 9732b719
......@@ -63,12 +63,10 @@ TOP_MODULE := {top_module}
self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n")
def get_stamp_file(self, file):
def get_stamp_file(self, dep_file):
"""Stamp file for source file :param file:"""
return os.path.join(
file.library,
file.purename,
".{}_{}".format(file.purename, file.extension()))
name = dep_file.purename
return os.path.join(dep_file.library, name, ".{}_{}".format(name, dep_file.extension()))
def _makefile_sim_sources_lang(self, name, klass):
"""Generic method to write the simulation Makefile HDL sources"""
......@@ -91,13 +89,9 @@ TOP_MODULE := {top_module}
self._makefile_sim_sources_lang("VERILOG", VerilogFile)
self._makefile_sim_sources_lang("VHDL", VHDLFile)
def _makefile_sim_dep_files(self):
"""Print dummy targets to handle file dependencies"""
def _makefile_sim_file_rule(self, file_aux):
"""Generate target and prerequisites for :param file_aux:"""
cwd = os.getcwd()
fileset = self.fileset.sort()
for file_aux in fileset:
# Consider only HDL files.
if isinstance(file_aux, tuple(self.HDL_FILES)):
self.write("{}: {}".format(self.get_stamp_file(file_aux), file_aux.rel_path()))
# list dependencies, do not include the target file
for dep_file in sorted(file_aux.depends_on, key=(lambda x: x.path)):
......@@ -109,6 +103,13 @@ TOP_MODULE := {top_module}
for dep_file in sorted(file_aux.included_files):
self.write(" \\\n{}".format(path_mod.relpath(dep_file, cwd)))
self.writeln()
def _makefile_sim_dep_files(self):
"""Print dummy targets to handle file dependencies"""
for file_aux in self.fileset.sort():
# Consider only HDL files.
if isinstance(file_aux, tuple(self.HDL_FILES)):
self._makefile_sim_file_rule(file_aux)
if isinstance(file_aux, VHDLFile):
command_key = 'vhdl'
elif isinstance(file_aux, VerilogFile):
......
......@@ -81,16 +81,11 @@ class MakefileVsim(MakefileSim):
self.writeln("VLOG_FLAGS := %s" % vlog_flags)
self.writeln("VMAP_FLAGS := %s" % vmap_flags)
def _get_stamp_file(self, dep_file):
name = dep_file.purename
return os.path.join(dep_file.library, name, ".{}_{}".format(name, dep_file.extension()))
def _makefile_sim_compilation(self):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
cwd = os.getcwd()
fileset = self.fileset
if self.manifest_dict.get("include_dirs") is None:
self.writeln("INCLUDE_DIRS :=")
......@@ -123,14 +118,7 @@ class MakefileVsim(MakefileSim):
self.write(" || {} {}\n\n".format(shell.del_command(), lib))
# rules for all _primary.dat files for sv
for vlog in fileset.filter(VerilogFile).sort():
self.write("%s: %s" % (self._get_stamp_file(vlog), vlog.rel_path()))
# list dependencies, do not include the target file
for dep_file in sorted(vlog.depends_on, key=(lambda x: x.path)):
if dep_file is not vlog:
self.write(" \\\n" + self._get_stamp_file(dep_file))
for dep_file in sorted(vlog.included_files):
self.write(" \\\n{}".format(path_mod.relpath(dep_file, cwd)))
self.writeln()
self._makefile_sim_file_rule(vlog)
compile_template = string.Template(
"\t\tvlog -work ${library} $$(VLOG_FLAGS) "
"${sv_option} $${INCLUDE_DIRS} $$<")
......@@ -143,14 +131,7 @@ class MakefileVsim(MakefileSim):
self.writeln()
# list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile).sort():
# each .dat depends on corresponding .vhd file
self.write("%s: %s" % (self._get_stamp_file(vhdl), vhdl.rel_path()))
# list dependencies, do not include the target file
for dep_file in sorted(vhdl.depends_on, key=(lambda x: x.path)):
if dep_file is vhdl:
continue
self.write(" \\\n" + self._get_stamp_file(dep_file))
self.writeln()
self._makefile_sim_file_rule(vhdl)
self.writeln("\t\tvcom $(VCOM_FLAGS) -work {} $< ".format(vhdl.library))
self.writeln("\t\t@" + shell.mkdir_command() +
" $(dir $@) && " + shell.touch_command() + " $@ \n\n")
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