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Hdlmake
Commit 98943d10 authored by Tristan Gingold's avatar Tristan Gingold
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makefilesim, makefilevsim: factorize code.

parent 9732b719
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Showing with 22 additions and 40 deletions
hdlmake/tools/makefilesim.py
View file @ 98943d10
...@@ -63,12 +63,10 @@ TOP_MODULE := {top_module} ...@@ -63,12 +63,10 @@ TOP_MODULE := {top_module}
self.writeln("#target for performing local simulation\n" self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n") "local: sim_pre_cmd simulation sim_post_cmd\n")
def get_stamp_file(self, file): def get_stamp_file(self, dep_file):
"""Stamp file for source file :param file:""" """Stamp file for source file :param file:"""
return os.path.join( name = dep_file.purename
file.library, return os.path.join(dep_file.library, name, ".{}_{}".format(name, dep_file.extension()))
file.purename,
".{}_{}".format(file.purename, file.extension()))
def _makefile_sim_sources_lang(self, name, klass): def _makefile_sim_sources_lang(self, name, klass):
"""Generic method to write the simulation Makefile HDL sources""" """Generic method to write the simulation Makefile HDL sources"""
...@@ -91,24 +89,27 @@ TOP_MODULE := {top_module} ...@@ -91,24 +89,27 @@ TOP_MODULE := {top_module}
self._makefile_sim_sources_lang("VERILOG", VerilogFile) self._makefile_sim_sources_lang("VERILOG", VerilogFile)
self._makefile_sim_sources_lang("VHDL", VHDLFile) self._makefile_sim_sources_lang("VHDL", VHDLFile)
def _makefile_sim_file_rule(self, file_aux):
"""Generate target and prerequisites for :param file_aux:"""
cwd = os.getcwd()
self.write("{}: {}".format(self.get_stamp_file(file_aux), file_aux.rel_path()))
# list dependencies, do not include the target file
for dep_file in sorted(file_aux.depends_on, key=(lambda x: x.path)):
if dep_file is file_aux:
# Do not depend on itself.
continue
self.write(" \\\n" + self.get_stamp_file(dep_file))
# Add included files
for dep_file in sorted(file_aux.included_files):
self.write(" \\\n{}".format(path_mod.relpath(dep_file, cwd)))
self.writeln()
def _makefile_sim_dep_files(self): def _makefile_sim_dep_files(self):
"""Print dummy targets to handle file dependencies""" """Print dummy targets to handle file dependencies"""
cwd = os.getcwd() for file_aux in self.fileset.sort():
fileset = self.fileset.sort()
for file_aux in fileset:
# Consider only HDL files. # Consider only HDL files.
if isinstance(file_aux, tuple(self.HDL_FILES)): if isinstance(file_aux, tuple(self.HDL_FILES)):
self.write("{}: {}".format(self.get_stamp_file(file_aux), file_aux.rel_path())) self._makefile_sim_file_rule(file_aux)
# list dependencies, do not include the target file
for dep_file in sorted(file_aux.depends_on, key=(lambda x: x.path)):
if dep_file is file_aux:
# Do not depend on itself.
continue
self.write(" \\\n" + self.get_stamp_file(dep_file))
# Add included files
for dep_file in sorted(file_aux.included_files):
self.write(" \\\n{}".format(path_mod.relpath(dep_file, cwd)))
self.writeln()
if isinstance(file_aux, VHDLFile): if isinstance(file_aux, VHDLFile):
command_key = 'vhdl' command_key = 'vhdl'
elif isinstance(file_aux, VerilogFile): elif isinstance(file_aux, VerilogFile):
......
hdlmake/tools/makefilevsim.py
View file @ 98943d10
...@@ -81,16 +81,11 @@ class MakefileVsim(MakefileSim): ...@@ -81,16 +81,11 @@ class MakefileVsim(MakefileSim):
self.writeln("VLOG_FLAGS := %s" % vlog_flags) self.writeln("VLOG_FLAGS := %s" % vlog_flags)
self.writeln("VMAP_FLAGS := %s" % vmap_flags) self.writeln("VMAP_FLAGS := %s" % vmap_flags)
def _get_stamp_file(self, dep_file):
name = dep_file.purename
return os.path.join(dep_file.library, name, ".{}_{}".format(name, dep_file.extension()))
def _makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Write a properly formatted Makefile for the simulator. """Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules, The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool. etc are defined by the specific tool.
""" """
cwd = os.getcwd()
fileset = self.fileset fileset = self.fileset
if self.manifest_dict.get("include_dirs") is None: if self.manifest_dict.get("include_dirs") is None:
self.writeln("INCLUDE_DIRS :=") self.writeln("INCLUDE_DIRS :=")
...@@ -123,14 +118,7 @@ class MakefileVsim(MakefileSim): ...@@ -123,14 +118,7 @@ class MakefileVsim(MakefileSim):
self.write(" || {} {}\n\n".format(shell.del_command(), lib)) self.write(" || {} {}\n\n".format(shell.del_command(), lib))
# rules for all _primary.dat files for sv # rules for all _primary.dat files for sv
for vlog in fileset.filter(VerilogFile).sort(): for vlog in fileset.filter(VerilogFile).sort():
self.write("%s: %s" % (self._get_stamp_file(vlog), vlog.rel_path())) self._makefile_sim_file_rule(vlog)
# list dependencies, do not include the target file
for dep_file in sorted(vlog.depends_on, key=(lambda x: x.path)):
if dep_file is not vlog:
self.write(" \\\n" + self._get_stamp_file(dep_file))
for dep_file in sorted(vlog.included_files):
self.write(" \\\n{}".format(path_mod.relpath(dep_file, cwd)))
self.writeln()
compile_template = string.Template( compile_template = string.Template(
"\t\tvlog -work ${library} $$(VLOG_FLAGS) " "\t\tvlog -work ${library} $$(VLOG_FLAGS) "
"${sv_option} $${INCLUDE_DIRS} $$<") "${sv_option} $${INCLUDE_DIRS} $$<")
...@@ -143,14 +131,7 @@ class MakefileVsim(MakefileSim): ...@@ -143,14 +131,7 @@ class MakefileVsim(MakefileSim):
self.writeln() self.writeln()
# list rules for all _primary.dat files for vhdl # list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile).sort(): for vhdl in fileset.filter(VHDLFile).sort():
# each .dat depends on corresponding .vhd file self._makefile_sim_file_rule(vhdl)
self.write("%s: %s" % (self._get_stamp_file(vhdl), vhdl.rel_path()))
# list dependencies, do not include the target file
for dep_file in sorted(vhdl.depends_on, key=(lambda x: x.path)):
if dep_file is vhdl:
continue
self.write(" \\\n" + self._get_stamp_file(dep_file))
self.writeln()
self.writeln("\t\tvcom $(VCOM_FLAGS) -work {} $< ".format(vhdl.library)) self.writeln("\t\tvcom $(VCOM_FLAGS) -work {} $< ".format(vhdl.library))
self.writeln("\t\t@" + shell.mkdir_command() + self.writeln("\t\t@" + shell.mkdir_command() +
" $(dir $@) && " + shell.touch_command() + " $@ \n\n") " $(dir $@) && " + shell.touch_command() + " $@ \n\n")
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