Commit 9308e8ba authored by Tristan Gingold's avatar Tristan Gingold

testsuite: add a test for icarus include.

parent a94820ca
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
IVERILOG_OPT :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \
VHDL_SRC :=
VHDL_OBJ :=
simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)
iverilog $(IVERILOG_OPT) -s $(TOP_MODULE) -o $(TOP_MODULE).vvp -c run.command
include_dirs:
echo "# IVerilog command file, generated by HDLMake" > run.command
echo "+incdir+inc" >> run.command
work/macros/.macros_v: inc/macros.v
work/vlog/.vlog_v: vlog.v \
work/macros/.macros_v
echo $< >> run.command
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) run.command ivl_vhdl_work work
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.vvp
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="iverilog"
top_module = "gate"
include_dirs = ['inc']
files = [ "vlog.v"]
`include "macros.v"
module gate;
initial
$display("hello");
endmodule
......@@ -126,9 +126,12 @@ def test_isim_windows():
hdlmake.main.hdlmake([])
compare_makefile_xilinx()
def test_icarus():
def test_icarus_012():
run_compare(path="012icarus")
def test_icarus_include_083():
run_compare(path="083icarus_include")
def test_libero():
run_compare(path="013libero")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment