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Hdlmake
Commit 92927ed1 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Grab standard libs from the selected tool and use them in the solve process

parent 4a0efc02
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Showing with 58 additions and 46 deletions
hdlmake/__init__.py
View file @ 92927ed1
"""This file is the entry point for the complete HDLMake package"""
hdlmake/__main__.py
View file @ 92927ed1
......@@ -205,9 +205,6 @@ def _get_parser():
dest="reverse",
default=False,
action="store_true")
synthesis_proj = subparsers.add_parser(
"project",
help="create/update a project for the appropriated tool")
tree = subparsers.add_parser(
"tree",
help="generate a module hierarchy tree")
......
hdlmake/action/action.py
View file @ 92927ed1
......@@ -116,12 +116,12 @@ class Action(list):
logging.debug("End build complete file set")
return all_manifested_files
def build_file_set(self, top_entity=None):
def build_file_set(self, top_entity=None, standard_libs=None):
"""Build file set with only those files required by the top entity"""
logging.debug("Begin build file set for %s", top_entity)
all_files = self.build_complete_file_set()
if not self._deps_solved:
dep_solver.solve(all_files)
dep_solver.solve(all_files, standard_libs=standard_libs)
self._deps_solved = True
from hdlmake.srcfile import SourceFileSet
source_files = SourceFileSet()
......
hdlmake/action/simulation.py
View file @ 92927ed1
......@@ -79,7 +79,8 @@ class ActionSimulation(Action):
sys.exit("Exiting")
logging.info("Generating " + name + " makefile for simulation.")
top_module = self.get_top_module()
fset = self.build_file_set(top_module.manifest_dict["sim_top"])
fset = self.build_file_set(top_module.manifest_dict["sim_top"],
standard_libs=tool_object.STANDARD_LIBS)
dep_files = fset.filter(DepFile)
# dep_solver.solve(dep_files)
# tool_object.generate_simulation_makefile(dep_files, top_module)
......
hdlmake/action/synthesis.py
View file @ 92927ed1
......@@ -93,7 +93,8 @@ class ActionSynthesis(Action):
else:
tool_path = ""
top_mod = self.get_top_module()
fileset = self.build_file_set(top_mod.manifest_dict["syn_top"])
fileset = self.build_file_set(top_mod.manifest_dict["syn_top"],
standard_libs=tool_object.STANDARD_LIBS)
sup_files = self.build_complete_file_set()
privative_files = []
for file_aux in sup_files:
......
hdlmake/new_dep_solver.py
View file @ 92927ed1
......@@ -40,7 +40,7 @@ class DepParser(object):
"""Base dummy interface method for the HDL parse execution"""
raise
def solve(fileset):
def solve(fileset, standard_libs=None):
"""Function that Parses and Solves the provided HDL fileset. Note
that it doesn't return a new fileset, but modifies the original one"""
from .srcfile import SourceFileSet
......@@ -79,10 +79,20 @@ def solve(fileset):
'\n'.join([file_aux.path for
file_aux in list(satisfied_by)]))
elif len(satisfied_by) == 0:
logging.warning(
"Relation %s in %s not satisfied by any source file",
str(rel), investigated_file.name)
not_satisfied += 1
# if relation is a USE PACKAGE, check against provided standard dlibs
required_lib = rel.obj_name.split('.')[0]
if (not standard_libs is None and
required_lib in standard_libs and
rel.direction is DepRelation.USE and
rel.rel_type is DepRelation.PACKAGE):
logging.debug("Not satisfied relation %s in %s will be covered "
"by the target compiler standard libs.",
str(rel), investigated_file.name )
else:
logging.warning(
"Relation %s in %s not satisfied by any source file",
str(rel), investigated_file.name)
not_satisfied += 1
logging.debug("SOLVE END")
if not_satisfied != 0:
logging.warning(
......@@ -90,7 +100,7 @@ def solve(fileset):
not_satisfied)
else:
logging.info(
"Dependencies solved, all of the relations weres satisfied!")
"Dependencies solved, all of the relations were satisfied!")
def make_dependency_sorted_list(fileset, reverse=False):
......
hdlmake/tools/active_hdl.py
View file @ 92927ed1
......@@ -37,6 +37,8 @@ class ToolActiveHDL(ToolSim):
'windows_bin': 'vsimsa',
'linux_bin': None}
STANDARD_LIBS = ['ieee', 'std']
HDL_FILES = [VHDLFile, VerilogFile, SVFile]
CLEAN_TARGETS = {'clean': ["run.command", "library.cfg", "work"],
......
hdlmake/tools/diamond.py
View file @ 92927ed1
......@@ -27,8 +27,6 @@
from .make_syn import ToolSyn
from hdlmake.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile
DIAMOND_STANDARD_LIBS = ['ieee', 'std']
class ToolDiamond(ToolSyn):
......@@ -43,6 +41,8 @@ class ToolDiamond(ToolSyn):
SUPPORTED_FILES = [EDFFile, LPFFile]
STANDARD_LIBS = ['ieee', 'std']
HDL_FILES = [VHDLFile, VerilogFile]
CLEAN_TARGETS = {'clean': ["*.sty", "$(PROJECT)", "run.tcl"],
......
hdlmake/tools/ghdl.py
View file @ 92927ed1
......@@ -28,8 +28,6 @@ import string
from .make_sim import ToolSim
from hdlmake.srcfile import VHDLFile
GHDL_STANDARD_LIBS = ['ieee', 'std']
class ToolGHDL(ToolSim):
......@@ -41,6 +39,8 @@ class ToolGHDL(ToolSim):
'windows_bin': 'ghdl',
'linux_bin': 'ghdl'}
STANDARD_LIBS = ['ieee', 'std']
HDL_FILES = [VHDLFile]
CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)"],
......
hdlmake/tools/ise.py
View file @ 92927ed1
......@@ -57,6 +57,10 @@ class ToolISE(ToolSyn):
'linux_bin': 'xtclsh ',
'project_ext': 'xise'}
STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
SUPPORTED_FILES = [UCFFile, CDCFile, NGCFile]
HDL_FILES = [VHDLFile, VerilogFile, SVFile]
......
hdlmake/tools/isim.py
View file @ 92927ed1
......@@ -35,13 +35,6 @@ from hdlmake.util import path as path_mod
from hdlmake.srcfile import VerilogFile, VHDLFile
ISIM_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
class ToolISim(ToolSim):
"""Class providing the interface for Xilinx ISim simulator"""
......@@ -52,6 +45,12 @@ class ToolISim(ToolSim):
'windows_bin': 'isimgui',
'linux_bin': 'isimgui'}
STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
HDL_FILES = [VerilogFile, VHDLFile]
CLEAN_TARGETS = {'clean': ["./xilinxsim.ini $(LIBS)", "fuse.xmsgs",
......
hdlmake/tools/iverilog.py
View file @ 92927ed1
......@@ -29,13 +29,6 @@ from .make_sim import ToolSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
IVERILOG_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
class ToolIVerilog(ToolSim):
"""Class providing the interface for Icarus Verilog simulator"""
......@@ -46,6 +39,12 @@ class ToolIVerilog(ToolSim):
'windows_bin': 'iverilog',
'linux_bin': 'iverilog'}
STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
HDL_FILES = [VerilogFile, VHDLFile, SVFile]
CLEAN_TARGETS = {'clean': ["run.command", "ivl_vhdl_work"],
......
hdlmake/tools/libero.py
View file @ 92927ed1
......@@ -28,9 +28,6 @@ from .make_syn import ToolSyn
from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
LIBERO_STANDARD_LIBS = ['ieee', 'std']
class ToolLibero(ToolSyn):
"""Class providing the interface for Microsemi Libero IDE synthesis"""
......@@ -42,6 +39,8 @@ class ToolLibero(ToolSyn):
'linux_bin': 'libero SCRIPT:',
'project_ext': 'prjx'}
STANDARD_LIBS = ['ieee', 'std']
SUPPORTED_FILES = [SDCFile, PDCFile]
HDL_FILES = [VHDLFile, VerilogFile]
......
hdlmake/tools/modelsim.py
View file @ 92927ed1
......@@ -29,9 +29,6 @@ import os
from .sim_makefile_support import VsimMakefileWriter
MODELSIM_STANDARD_LIBS = ['ieee', 'std', 'altera_mf']
class ToolModelsim(VsimMakefileWriter):
"""Class providing the interface for Mentor Modelsim simulator"""
......@@ -41,6 +38,8 @@ class ToolModelsim(VsimMakefileWriter):
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
STANDARD_LIBS = ['ieee', 'std', 'altera_mf']
CLEAN_TARGETS = {'clean': ["./modelsim.ini", "transcript"],
'mrproper': ["*.vcd", "*.wlf"]}
......
hdlmake/tools/planahead.py
View file @ 92927ed1
......@@ -27,9 +27,6 @@ from .xilinx import ToolXilinx
from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile, XCOFile)
PLANAHEAD_STANDARD_LIBS = ['ieee', 'std']
class ToolPlanAhead(ToolXilinx):
"""Class providing the interface for Xilinx PlanAhead synthesis"""
......@@ -41,6 +38,9 @@ class ToolPlanAhead(ToolXilinx):
'linux_bin': 'planAhead -mode tcl -source ',
'project_ext': 'ppr'}
STANDARD_LIBS = ['ieee', 'ieee_proposed', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
SUPPORTED_FILES = [UCFFile, NGCFile, XMPFile, XCOFile]
CLEAN_TARGETS = {'clean': ["planAhead_*", "planAhead.*", "run.tcl",
......
hdlmake/tools/quartus.py
View file @ 92927ed1
......@@ -34,9 +34,6 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
QUARTUS_STANDARD_LIBS = ['altera', 'altera_mf', 'lpm', 'ieee', 'std']
class ToolQuartus(ToolSyn):
"""Class providing the interface for Altera Quartus synthesis"""
......@@ -48,6 +45,8 @@ class ToolQuartus(ToolSyn):
'linux_bin': 'quartus -t ',
'project_ext': 'qsf'}
STANDARD_LIBS = ['altera', 'altera_mf', 'lpm', 'ieee', 'std']
SUPPORTED_FILES = [SignalTapFile, SDCFile, QIPFile, QSYSFile, DPFFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile]
......
hdlmake/tools/riviera.py
View file @ 92927ed1
......@@ -72,6 +72,8 @@ class ToolRiviera(VsimMakefileWriter):
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
STANDARD_LIBS = RIVIERA_STANDARD_LIBS
CLEAN_TARGETS = {'clean': ["*.asdb"],
'mrproper': ["*.vcd"]}
......
hdlmake/tools/vivado.py
View file @ 92927ed1
......@@ -29,9 +29,6 @@ from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile,
XCOFile, BDFile, TCLFile)
VIVADO_STANDARD_LIBS = ['ieee', 'std']
class ToolVivado(ToolXilinx):
"""Class providing the interface for Xilinx Vivado synthesis"""
......@@ -44,6 +41,8 @@ class ToolVivado(ToolXilinx):
'project_ext': 'xpr'
}
STANDARD_LIBS = ['ieee', 'std']
SUPPORTED_FILES = [UCFFile, NGCFile, XMPFile,
XCOFile, BDFile, TCLFile]
......
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